F Vahid, D Gajski, "Incremental hardware estimation during hardware/software functional partitioning", IEEE Trans. VLSI, V-3, 1995  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... (such as SDF [16] or DDF [9] in this work we target heterogeneous controldominated embedded system applications, so we assume a functional decomposition that captures the design as a network of Finite State Machine modules extended with data computation (EFSMs) as described in [7] and [21]. Each module behavior is conveyed using graphical entry or an FSM based reactive language (for example Esterel [6] front end. We focus on the representation, optimization, and synthesis of each individual task in the network, so we do not assume a specific model of computation governing the ....

Vahid, F., Gajski, D. "Incremental Hardware Estimation During Hardware/Software Functional Partitioning", IEEE Transactions on VLSI Systems, Sept. 1995.

....goals of low hardware effort and timing constraints by accepting all hardware efforts below a given size rather than trying to optimize hardware effort and timing at the same time. They use an incremental algorithm for estimating hardware effort that is adapted to function level partitioning [5]. Our approach handles the contradictory goals of minimizing hardware and meeting real time constraints by a cost function that is dynamically weighted rather than selecting from a set of different cost functions. III. A HIGH LEVEL HARDWARE EFFORT ESTIMATION TECHNIQUE The aim of this hardware ....

....for the controller and the memory. However, statistical assumptions may lead Fig. 1. Components to estimate: Registers, input multiplexer, modules and output multiplexer to larger deviations. Furthermore, it is not assumed that a scheduling has already been performed. The method introduced in [5] is one of the few that is tailored to the demands of hardware software co design since it features an incremental estimation for each possible hardware software partitioning. The method is accurate for coarse grain estimation (e.g. estimating whole functions or tasks) but inaccurate for ....

F. Vahid, D.D. Gajski, Incremental Hardware Estimation during Hardware/Software Functional Partitioning, IEEE Trans. on VLSI Systems, Vol.3, No.3, pp. 459-- 464, Sept. 1995.

....problem that has many applications, particularly in the semiconductor design process. Higher levels of integration emphasizes a need for even more logical and physical level partitioning. Partitioning is the only synthesis task conducted at all levels of design process, from the system [Gup90, Kal97, Vah95] and behavioral levels [Geu91] to the logic synthesis [Bea92, Dey91] and physical design levels [Alp95] Partitioning also plays an important role in design analysis: it is widely studied in the simulation [Con94. Tha92] manufacturing, testing [Sri91] and emulation [But95] literature. Outside of ....

F. Vahid and D.D. Gajski. Incremental hardware estimation during hardware/software functional partitioning. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Sept. 1995, vol.3, (no.3):459-464. 18

....show the superiority of behavioral over structural partitioning. A behavioral partitioner has no a priori knowledge about design parameters such as area and latency. The partitioner must be guided by a high level estimator that provides the required information. Efficient estimation techniques [2, 3] have been developed for this purpose. The approach presented in [2] presents an efficient design space exploration technique that can be performed dynamically with partitioning. A partitioner can effectively control the trade off between the execution time and the design space This work is ....

F. Vahid and D. Gajski. "Incremental Hardware Estimation During Hardware/Software Functional Partitioning". In IEEE Transactions on VLSI Systems, volume 3, September 1995.

....needed is calculated to guarantee the shortest latency. Based on the calculated hardware resources, the area of the application specific circuit is estimated. To map more than one node of the control flow graph on one specific hardware implementation, the estimation algorithm described in [29] is used. For estimating software execution times, a different algorithm calculates the latency of the given data flow graph based on a restricted number of resources (registers ALUs) with fixed costs. After synthesis and implementation on the prototyping board, the execution times calculated by ....

F.Vahid, D.D. Gajski. Incremental Hardware Estimation during Hardware/Software Functional Partitioning. IEEE Transactions on VLSI-Systems, Vol. 3, No. 3, Sept. 1995

....all time constraints. The target architecture template is used as a constraint during co synthesis and can be adapted by the user for design space exploration. The application specific hardware costs are estimated on a scheduling block basis with an approach that is based on earlier work in [21]. As mentioned, partitioning supports different levels of granularity. There are two reasons not to fix granularity. First, and already explained, finer granularity offers a higher optimization potential. Second, static non preemptive scheduling can support shorter process periods and process ....

F. Vahid, D.D. Gajski, Incremental Hardware Estimation during Hardware/Software Functional Partitioning, IEEE Trans. on VLSI Systems, Vol. 3, No. 3, S 459-464, Sept. 1995.

....requirements are have the most impact on the hardware software partition in this case. In [16] hardware software partitioning is performed with an eye toward performance requirements, implementation cost, and, to some extent, concurrency. Furthermore, the implementation cost formulation [18] considers the potential for sharing resources among the set of functions implemented in hardware, which further complicates the partitioning problem. microprocessor native code storage co processor interface logic ctrl ctrl path data path data software hardware Figure 9: A multi threaded custom ....

F. Vahid and D. D. Gajski, "Incremental Hardware Estimation During Hardware/Software Functional Partitioning," IEEE Transactions on VLSI Systems, vol. 3, no. 3, 1995.

....number of bits and words for each storage unit, the number of bits and type of each functional unit, the number of sources of each storageunit input, functional unit input, and data path output, the number of data path connections, and the number of data path components. For example functions, see [31]. a) Preestimation: The parameters are computed for each functional object during preestimation, by performing rough synthesis on each object. Each object is then annotated with the computed parameters. Such computation can take seconds or GAJSKI et al. SPECSYN: AN ENVIRONMENT SUPPORTING THE SER ....

....determine the number of FU s by taking the union of the objects FU s (since sequential behaviors can share FU s) Note that the terms, such as state register size and number of FU s, are not obtained by simple addition; in fact, terms may actually be nonlinear with respect to the parameters. See [31] for details on computing all the terms from the objects parameters. b) Online estimation: When a partitioning heuristic removes an object from a processor, we update that processor s terms. Some terms can be updated simply by examining the object s annotations. For example, the number of ....

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F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," IEEE Trans. VLSI Syst., vol. 3, pp. 459--464, Sept. 1995.

....or exlined to adjust the granularity) It is achieved by using any of several heuristics (such as simulated annealing, a modified Kernighan Lin heuristic, clustering or greedy improvement) or by manually moving objects. For further details on the partitioning approach, the reader is referred to [19, 4, 12, 20]. In addition to using the SLIF representation, our approach uses the FunctionBus for inter part communication [18] In contrast, many earlier multipackage functional partitioning approaches used a cut edges approach to I O implementation. In such an approach, a graph s nodes, representing ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning, " IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....can be hard. In contrast, in structural partitioning, we can easily estimate size and and delay quickly and accurately, by summing object sizes and counting critical path cuts. However, sophisticated estimation techniques for use with functional partitioning can help alleviate this drawback [16]. Second, a functionally partitioned system often (though not always, as we shall see) uses more gates, since hardware units are not shared by functions on different parts. However, structural partitioning is I O dominated and hence does not use all the gates on a part anyways, so this increase is ....

....procedures or functions, statement blocks, statements, or even fine grained arithmetic operations. These atomic objects will be assigned to parts during partitioning. Fine granularities yield more partitioning choices, but require longer heuristic runtimes and result in less accurate estimations [16]. Many systems partition at the granularity of arithmetic operations [10, 11, 30, 12] Partitioning heuristics can be classified as either iterative improvement or constructive heuristics. Constructive heuristics start with no initial partition, and build a partition. A common constructive ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning, " IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....number of bits and words for each storage unit, the number of bits and type of each functional unit, the number of sources of each storage unit input, functional unit input, and datapath output, the number of datapath connections, and the number of datapath components. For example functions, see [31]. Pre estimation The parameters are computed for each functional object during pre estimation, by performing rough synthesis on each object. Each object is then annotated with the computed parameters. Such computation can take seconds or minutes. Given an initial partition of functional ....

....determine the number of FU s by taking the union of the objects FU s (since sequential behaviors can share FU s) Note that the terms, such as state register size and number of FU s, are not obtained by simple addition; in fact, terms may actually be non linear with respect to the parameters. See [31] for details on computing all the terms from the objects parameters. Online estimation When a partitioning heuristic removes an object from a processor, we update that processor s terms. Some terms can be updated simply by examining the object s annotations. For example, the number of ....

[Article contains additional citation context not shown here]

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning, " IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....occurs only once at the beginning of exploration and is independent of any particular partition and allocation. 2. Online estimation: Pre estimated annotations are combined in complex expressions to rapidly obtain metric values for a particular partition and allocation (usually in constant time [14]) Online estimation occurs hundreds or thousands of times during manual or automated exploration. In most other approaches, exploration consists of only one level of estimation, with another level coming only after RT level design. We now discuss SpecSyn estimation models for three metric types: ....

....DP components is a function of area factor Fig. 9: Equation and terms for computing CU DP area 4.3.2 Hardware size SpecSyn uses a hardware design model similar to those in [11, 16, 17] consisting of a control unit datapath (CU DP) as shown in Figure 8. We present our estimation technique [14] briefly here. The CU DP area can be computed as the sum of the following terms: Functional unit (FU) size; Storage unit size including registers, register files and memories; Multiplexer size; State register size; Control logic size; and Wiring size. As shown in Figure 9, each term is a func ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning, " IEEE Transactions on VLSI Systems, vol. 3, no. 3, pp. 459--464, 1995.

....through the use of shift registers, simple distributed controllers, and multiple clocks. Our approach is very different as it is based on functional partitioning, whose advantages were listed earlier. Functional partitioning techniques are complex and have appeared in many earlier publications [12, 19, 20, 21, 26, 27], so we do not describe such techniques here. Instead, we demonstrate the ability to tradeoff I O and performance when using the FunctionBus, by varying the bus size and hence making serial versus parallel communication tradeoffs. In the remainder of this paper, we describe the problem, summarize ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....good size and performance estimates quickly can be hard. In contrast, in structural partitioning, we can easily estimate size and and delay quickly and accurately, by summing object sizes and counting critical path cuts. However, sophisticated estimation techniques can help alleviate this drawback [15]. Second, a functionally partitioned system often (though not always, as we shall see) uses more gates, since hardware objects aren t shared by functions on different parts. However, since partitioning is often I O dominated, this increase is often insignificant. Another problem solvable with ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning, " IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....estimators, and synthesis tools, but is beyond the scope of this paper. Discussions regarding estimation techniques and accuracies can be found in [5, 17] For a discussion on a more complex method for hardware size estimation, which considers hardware sharing among functional objects, see [18]. 3 Kernighan Lin heuristic background An improvement heuristic is one that, given an initial partition, moves nodes among parts seeking a lower cost partition. Cost is measured using a cost function. A move is a displacement of a node from one part (e.g. a chip) to another part. Such ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 3, pp. 459--464, 1995.

....to [19] We also point out that annotations can be much more complex than just numbers, to account for interaction between nodes when implemented on the same component. For example, complex annotations for performing hardware size estimation while accounting for hardware sharing are described in [20]. Note that annotations provide a simple means to override an estimation; the user just changes the annotation. They also provide a means for partitioning in the absence of a complete specification; the user can create an empty procedure, and then provide necessary annotations manually. 4 ....

....to generate the ict of hardware above. 4.4.2 Size We now consider generating a size value for each node. We use the same approach as used for ict. Specifically, we first examine the distribution of hardware sizes for the nodes of the real examples, where node size is determined as described in [19, 20]. The distribution is shown in Figure 11 with intervals of 500 gates. Node sizes ranged between Ex Nodes Regression equation Corr. ANS 44 ict hw = 1.12 0.0404 ict sw 0.58 ETHER 124 ict hw = 0.228 0.0220 ict sw 0.92 FUZZY 69 ict hw = 0.24 0.0191 ict sw 0.98 ITV 84 ict hw = 0.070 ....

F. Vahid and D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," in IEEE Transactions on Very Large Scale Integration Systems, pp. 459--464, 1995.

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F Vahid, D Gajski, "Incremental hardware estimation during hardware/software functional partitioning", IEEE Trans. VLSI, V-3, 1995

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F. Vahid and D. D. Gajski, "Incremental hardware estimation during hardware/software functional partitioning," IEEE Trans. VLSI Syst., vol. 3, pp. 459--464, Mar. 1995.

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F. Vahid and D.D. Gajski. Incremental hardware estimation during hardware/software functional partitioning. IEEE Transactions on VLSI Systems, 3(6):459--464, September 1995.

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