Rajvie Bagrodia, Yu an Chen, Vikas Jha, and Nicki Sonpar. Parallel Gate-level Circuit Simulatin on Shared Memory Architecutres. In Proceedings of the IEEE Intl. Conf. on Computer-Aided Design, October 1995. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
PARALLEL SWITCH-LEVEL SIMULATION of VLSI CIRCUITS - Chen, Jha, Bagrodia (1995) Self-citation (Bagrodia Chen Jha) (Correct)
....the IBM SP1. Maisie implementations have yielded good speedups for queuing network benchmarks with both conservative and optimistic algorithms, with speedups approaching close to linear for large grain computations[18, 2] The IBM SP1 implementations have been used for gate level circuit simulations[6, 5] and for simulation of parallel programs[23] The MIRSIM program contains a driver entity and one other entity type called irsim. The driver entity initiates the simulation by instantiating a set of irsim entities. The circuit to be simulated is partitioned into a number of subcircuits and each ....
Rajvie Bagrodia, Yu an Chen, Vikas Jha, and Nicki Sonpar. Parallel Gate-level Circuit Simulatin on Shared Memory Architecutres. In Proceedings of the IEEE Intl. Conf. on Computer-Aided Design, October 1995.
Parallel Switch-Level Simulation of VLSI Circuits - Chen, Jha, Bagrodia (1995) (Correct)
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Rajvie Bagrodia, Yu an Chen, Vikas Jha, and Nicki Sonpar. Parallel Gate-level Circuit Simulatin on Shared Memory Architecutres. In Proceedings of the IEEE Intl. Conf. on Computer-Aided Design, October 1995.
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