Auguin M., Boeri F., and Carriere C., "Automatic exploration of VLIW processor architectures from a designer's experience based specification", 3rd Int'l. Workshop on Hardware/Software Codesign, pp. 108--115, Grenoble, France, September 1994. Home/Search Document Details and Download
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Custom Embedded Counterflow Pipelines - Childers (2000) (Correct)
....and affect critical path latencies. Indeed, the first PipeRench prototype devotes nearly 50 of chip area to configuration memory. 2.4. 3 Application Specific Processors There have been numerous proposals for designing processors tailored to the resource requirements of embedded applications [Auguin94,DeGloria90,Holmer91,Huang92]. These proposals typically use an architecture template to instantiate a custom processor. The template makes it easy to parameterize a custom architecture: the number and type of functional units and the interconnection topology can be customized to an application by changing architectural ....
Auguin M., Boeri F., and Carriere C., "Automatic exploration of VLIW processor architectures from a designer's experience based specification", 3rd Int'l. Workshop on Hardware/Software Codesign, pp. 108--115, Grenoble, France, September 1994.
VLIW Processor Codesign for Video Processing - Wilberg, Camposano (1997) (7 citations) (Correct)
....ES design. The references are grouped according their main focus of interest. Topics References Specification, Verification ASAR [6] A.Benveniste, G. Berry [9] Codes [12] Cosmos [42] 49] Simulation Insulin [105] Ptolemy [13] 53] J.A. Rowson [93] B. Kerridge [56] Code Generation Capsys [5]; Chess [58] CodeSyn [64] C. Monahan, F. Brewster [70] MOVE [36] Oscar [57] PEAS 1 [2] Analysis ADAM [48] X. Hu [37] J. Gong, et al. 29] Partitioning Cosyma [21] 34] A. Kalavade , E.A. Lee [54] K.A. Olukotun, et al. 78] Tosca [3] Vulcan [32] 31] Case Studies GPS [102] 101] ....
.... the result to a simulation object which mimics the pipelined behavior of the functional 24 static void void SIRcrt0 ( r3, r4, r5 ) Block0: profBasicBlock(Functioncrt0, 0) predecessors: successors: simInst( r[32] r[3] simInst( r[34] r[4] simInst( r[33] r[5]; simInst( mem[SIRdataLabelenviron] r[33] simInst( globalctors( simInst( r[3] SIRdataLabelglobaldtors; simInst( atexit( simInst( r[3] r[32] simInst( r[4] r[34] simInst( r[5] r[33] Figure 9. Example of the generated C C based assembler code for the compiled ....
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M. Auguin, F. Boeri, and C. Carriere. Automatic exploration of VLIW processor architectures from a designer's experience based specification. In 3rd Int. Workshop on Hardware /Software Codesign, pages 108--115, Sept. 22-23, Grenoble, September 1994.
Codesign for Real-Time Video Applications - Wilberg (1996) (1 citation) (Correct)
....for the research on retargetable compilers: in case of DSPs, the existing compilers are often not good enough, and in case of ASIPs (Application Specific Instruction Set Processors) the complexity makes manual programming a tedious and error prone task. INTRODUCTION 7 Mimola [ 132] and Capsys [ 10] generate firmware for VLIW processors. The Capsys system can directly process C code. The PEAS 1 [ 4] system uses a modification of machine descriptions in the GNU gcc to produce opcode for a newly designed processor. This approach also allows to process C code, but only a RISC like scalar ....
M. Auguin, F. Boeri, and C. Carriere. Automatic exploration of VLIW processor architectures from a designer's experience based specification. 172 CODESIGN FOR REAL-TIME VIDEO APPLICATIONS In 3rd Int. Workshop on Hardware/Software Codesign, pages 108--115, Sept. 22-23, Grenoble, September 1994.
A Design Example Using CASTLE - Plöger, Wilberg (Correct)
....we base our processor on a VLIW processor architecture. This architecture relies on the compiler for parallelizing the instructions, thus achieving a high processing power with little hardware overhead for the controlling. This kind of architecture is also used for the Capsys design system [2], but the Capsys system does not include the generation of a compiler back end, instead the firmware for a particular application is produced. The generation of a C compiler was addressed in the PEAS 1 [1] but only for a RISC like scalar processor. The MOVE system developed at the Delft Technical ....
M. Auguin, F. Boeri, C. Carriere: "Automatic Exploration of VLIW Processor Architectures from a Designer's Experience Based Specification", 3rd Int. Workshop on Hardware/Software Codesign, Sept. 22-23, Grenoble, pp. 108-115, 1994.
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