J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, CA, 1993, pp. 142-151.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....used in emulators. Atypical emulation board consists of several FPGAs interconnected to 3 10 6 Cost ( Performance (Hz) COST PERFORMANCE Software Simulator (VCS, Modelsim) 10K 0.5M Our Approach Emulator (Axis, Tharas) ###### ## ###### ### ########## ### ########## gether. [3, 4] demonstrated the Virtual Wires scheme to time multiplex wires on physical pins connecting the FPGAs, thereby improving their utilization. However, such large emulation systems are neither cost e ectivenor scalable. Several emulation vendors use multiple FPGAs and specially designed hardware ....

J. Babb,R.Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In ########### ## ### #### ######## ## ##### ### ###### ######### ########,April 1993.

.... of such systems include the experimental DECPeRLe board [18] SPLASH 2 [8] Teramac [19] and the commercial WILD series from Annapolis Microsystems [20] Some software tools exist which can automatically partition the design between multiple FPGAs on a board using higher level abstractions [21]. For a detailed overview of FPGA devices and multi FPGA architectures see [5] SPLASH SPLASH and SPLASH 2 [8] its successor, can be conceptually viewed as a system of linear array of processing elements. This architecture makes SPLASH 2 a good candidate for systolic applications with limited ....

R. Tessier J. Babb and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," IEEE Workshop on FPGAs for Custom Computing Machines, April 1993.

....shortest path for routing a net, breadth first search is performed starting from the source FPGA and stopping once the target FPGA is reached. The TIERS algorithm also identifies critical nets and gives them higher priority to achieve as much as a factor of 2. 5 speed improvement over prior work [Babb93]. A different approach towards topology independent routing is adopted in [Kim96] For each topology, all possible routing paths (patterns) between every pair of FPGAs are stored. To minimize inter FPGA routing delays, only paths of length one or two hops are considered. When routing each net, ....

J. Babb et al, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....they frequently require a higher proportion of I O resources vs. logic in each chip than is normally required in singleFPGA use. For this reason, some research has focused on methods to allow pins of the FPGAs to be re used for multiple signals. This procedure is referred to as Virtual Wires [Babb93, Agarwal95, Selvidge95], and allows for a flexible trade off between logic and I O within a given multi FPGA system. Signals are multiplexed onto a single wire by using multiple virtual clock cycles, one per multiplexed signal, within a user clock cycle, thus pipelining the communication. In this manner, the I O ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....the North South axis. Given the regimen of two clock cycles per incoming pixel, communication can be duplexed. Hence, 86 bits can be communicated by multiplexing the outputs and inputs on these North South 43 pin connections. This approach is similar to the method used in the Virtual Wires machine [Babb93]. This multiplexing will be simplified by the Xilinx EX chips with their strobed I O registers and multiplexed I O pins. 4.3 Memory use A census transform requires several scanlines of data in order to form the census vector for a pixel in one cycle. The computation needs access to several pixels ....

J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, IEEE FPGAs for Custom Computing Engines, pp. 142-151, April 1993.

....as an extension of the physical FPGA device: the applications have a virtual view of the FPGA that is mapped on the available physical device by the operating system, in a way similar to virtual memory. In other words, the FPGA is virtualized by multiplexing its physical components. The same idea [9] has also been followed for increasing the number of FPGA I O pins, leading to the concept of virtual wires. In both cases the goal is to extend the capabilities of the FPGA devices. Physical Virtual layer Layer Fig. 1. Physical layer and Virtual layer: A virtual configurable logic block is ....

J. Babb, R. Tessier, A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines'93, 1993.

.... of such systems include the experimental DECPeRLe board [76] SPLASH 2 [19] and Teramac [1] and the commercial WILD series from Annapolis Microsystems [56] Some software tools exist which can automatically partition the design between multiple FPGAs on a board using higher level abstractions [42]. For a detailed overview of FPGA devices and multi FPGA architectures see [40] 21 2.2.1 SPLASH SPLASH and SPLASH 2 [19] its successor, can be conceptually viewed as a system of linear array of processing elements. This architecture makes SPLASH 2 a good candidate for systolic applications ....

R. T. J. Babb and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. IEEE Workshop on FPGAs for Custom Computing Machines, April 1993.

....as an extension of the physical FPGA device: the applications have a virtual view of the FPGA that is mapped on the available physical device by the operating system, in a way similar to virtual memory. In other words, the FPGA is virtualized by multiplexing its physical components. The same idea [10] has also been followed for increasing the number of FPGA I O pins, leading to the concept of virtual wires. In both cases the goal is to extend the capabilities of the FPGA devices. As opposed, we see a virtual FPGA as a simplified version of a physical FPGA. The idea is not to enhance the FPGA ....

J. Babb, R. Tessier, A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines'93, 1993.

....that he leveraged this filtering capability to display disassembled versions of programs as they executed on a processor implemented on Teramac; this was, of course, much easier than observing and deciphering the machine code that the processor executed. InnerView As a part of the Virtual Wires[29] logic emulation project, Silvina Hanono created the InnerView Hardware Debugger[30] for the Virtual Wires emulation board. The debugger had two significant features. First, the debugger leveraged the configuration readback capability of the Xilinx FPGAs in the Virtual Wires emulation system to ....

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators", in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D. A. Buell and K. L. Pocek, Eds., Napa, CA, Apr. 1993, pp. 142--151.

....the NorthSouth axis. Given the regimen of two clock cycles per incoming pixel, communication can be duplexed. Hence, 86 bits can be communicated by multiplexing the outputs and inputs on these North South 43 pin connections. This approach is similar to the method used in the Virtual Wires engines [Babb93]. This multiplexing will be simplified by the Xilinx EX chips with their strobed I O registers and multiplexed I O pins. 4.3 Memory use A census transform requires several scanlines of data in order to form the census vector for a pixel in one cycle. The computation needs access to several ....

J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, IEEE FPGAs for Custom Computing Engines, pp. 142-151, April 1993.

....inserted to handle some of the logic. If too many signals need to be routed along a given link, an extender card spanning several daughter card positions can be added, with new routing paths included on the inserted card. Note that while most routing limitations can be dealt with by Virtual Wires [Babb93], a method for multiplexing several circuit wires onto one physical connection, added cards for routing will reduce the reliance on Virtual Wires, thus decreasing both area and cycle time. For signals that must go long Device Device Device FPGA Device FPGA Daughter Card Device FPGA ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....packaging technology in its growth. Although the FPGA s can be clocked very fast (50 100 MHz) a hardware emulator usually runs very slowly (a few megahertz) because, during every emulation cycle, signals must travel through combinational paths across multiple FPGA s. Virtual wire technology [2], 5] 11] takes advantage of the high FPGA speed, with respect to the low emulation speed. By means of time division multiplexing (TDM) it uses each physical inter FPGA wire to transport several logical signals during each emulation cycle. In a virtual wire based emulator, an emulation cycle ....

....can easily have a logic capacity of more than 10 000 gates. However, the number of I O pins is restricted to a few hundred. For example, the largest chip from Xilinx (XC4025) 19] has 25 000 gates housed in a 299 pin package, of which only 256 are signal pins. III. VIRTUAL WIRING Babb et al. [2], 5] 11] proposed using a TDM scheme to increase the effective inter FPGA communication capability during hardware emulation. We use Fig. 2 to illustrate the operation principle of virtual wiring. Suppose the emulator is to run at 1 MHz, and the longest combinational path travels across six ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," in Proc. IEEE Workshop FPGA-Based Custom Computing Machines, Napa, CA, Apr. 1993, pp. 142--151.

.... hardware platform much simpler, smaller, and cheaper than an emulator, where inter FPGA communications is a complex problem requiring expensive solutions, such as hierarchical crossbar structures [33] or dedicated field programmable interconnect chips [23] or time multiplexing hardware [6]. Unlike multi FPGA partitioning techniques which have to deal with a specific board interconnect scheme, our decomposition is independent of the architecture of the target hardware platform. The lack of any inter FPGA interconnect also provides the basis for the virtual hardware mechanism: if we ....

J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGAbased Logic Emulators," Proc. Symp. on Field-Programmable Custom Computing Machines, pp. 142-151, April 1993

....of I O pins that enable data communication between two connected computing resources. Sharing ports among several channels defuses the problem of limited I O pin resources. Port sharing applies to external edges of the node types b and c and has been extensively used in the Virtual Wire project [2, 1]. We extend port sharing to time exclusive configurations of runtime reconfigurable systems. Therefore, we di#erentiate between two types of port sharing: Intraconfiguration port sharing allows communication channels in the same configuration to share I O ports by adding multiplexing and ....

....configurations of runtime reconfigurable systems. Therefore, we di#erentiate between two types of port sharing: Intraconfiguration port sharing allows communication channels in the same configuration to share I O ports by adding multiplexing and demultiplexing interface circuitry [1]. This technique can be applied to both CTR and RTR systems. Interconfiguration port sharing allows communication channels in di#erent configurations of one FPGA to share I O ports. These channels would otherwise be mapped to di#erent ports as configurations of other FPGAs could require that ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In IEEE Workshop on FPGA-based Custom Computing Machines, pages 142--151, Napa, CA, April 1993.

....Clos like X 12 XC3xxx bus Table 2.1: Partial list of emulators and prototyping boards describing interconnection architecture and chips supported. Some of the boards listed in the table use what we call pure interconnect structures, for example PeRLe0 [11] PeRLe1 [11] and Virtual Wires [16] all use a mesh architecture to implement the interconnection among FPGAs while the X 12 [17] of National Technologies Inc. uses a bus. The Anyboard [10] and Splash 1 [13] use a linear array. BORG [5] and ACME consist of user FPGAs connected together via a Clos like network, also implemented with ....

....the logic level (always referring to time) But this technique does not really help us for ACME, since the neurons are designed to process data in serial fashion. Time multiplexing is used as a means to reduce the number of pins required to implement a system and is used by Virtual Wires of MIT [16]. A specialized program has to insert extraneous logic at the edge of the user defined logic to enable the multiplexing and de multiplexing of signals (a chain of shift registers) The disadvantages of this implementation are that debugging with an oscilloscope is rendered almost impossible, and ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142--151, April 1993.

....for routing channels as implemented on a FPGA. The structures that occupy large area on FPGAs are reduced to a bare minimum using SRAM technology. Second, since the circuit evaluation is time multiplexed, it makes sense to time multiplex the interconnect as well. In the VirtualWires TM system [BTA93] [SADB95] small shift loops are added to the circuitry of partitions mapped into a FPGA based logic emulator. Each shift loop shifts the results of computations on one FPGA onto a wire bound for another FPGA where another loop of the same length demultiplexes the signals. The shift loops have a ....

J. Babb, R. Tessier and A. Agarwal. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proc. FPGAs for Custom Computing Machines, 1993, pp. 142-151.

....and variable board architectures, software techniques are used to make the design board independent. It becomes the partitioner and the synthesis tools responsibility to adapt the design to the RC architecture utilized. Several mechanisms exist to reuse pins for several connections; Virtual wires [12] offer a way of overcoming pin limitations in FPGAs by statically scheduling data transfers so that multiple transfers re use the same set of pins. This comes at the price of statically scheduling accesses. On the other hand, Vahid used functional partitioning and the concepts of FunctionBus ....

J. Babb, R. Tessier, A. Agarwal. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators". In Proceedings of FPGAs for Custom Computing Machines, 1993.

.... of such systems include the experimental DECPeRLe board [59] SPLASH 2 [15] and Teramac [1] and the commercial WILD series from Annapolis Microsystems [43] Some software tools exist which can automatically partition the design between multiple FPGAs on a board using higher level abstractions [35]. For a detailed overview of FPGA devices and multi FPGA architectures see [30] 2.2 Hybrid Architectures Configurable platforms which have shown impressive results typically have configurable logic attached to a host system through some interface such as the system bus or the I O channels. ....

R. Tessier J. Babb and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. IEEE Workshop on FPGAs for Custom Computing Machines, April 1993.

....clock cycle that is transported into or out of the cluster, respectively. The equation is based on the concept of port maps: the input and output variables are multiplexed through the same physical input or output port. 16 Lieverse et al. The effectiveness of this concept is shown for FPGAs in [4]. For every run to construct PEs when instantiating an architecture, three parameters can be given to influence the construction of the PEs: a maximum number of PEs, and a maximum number of input and output ports. These parameters are used as constraints for the PE definition. The number of ....

J.W. Babb. Virtual wires: Overcoming pin limitations in FPGA-based logic emulation. Master's thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1993.

....is that designs may be implemented using fewer FPGAs than would otherwise be the case. This technique presupposes, of course, that the system algorithm can be partitioned to facilitate this type of operation but there are enough algorithms amenable to the method to justify its development [2] [6]. The majority of current reconfigurable FPGAs, including the market leading LCA series devices from Xilinx Inc. can be used to realize reconfigurable systems. However, they exhibit three important restrictions: 1. When the FPGA is reconfigured to load a new circuit, the operation of the logic ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", In: D. Buell and K. Pocek (eds.), Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, Ca., pp 142-151, 1993.

....system responsible for the run time placement of tasks, it also needs 7 to ensure I O can be routed to the border and determine acceptable port locations for interfacing signals to off chip wires. The Virtual Wires project at MIT has developed techniques for time multiplexing the use of pins [1]. Internal wire resources are typically statically allocated and are at best space shared by segmenting their lengths. It may be desirable to allow these to be multiplexed as well. One possibility is to provide redundant links and implement slightly more sophisticated switches that would allow ....

Jonathan Babb, Russell Tessier, and Anant Agarwal. Virtual wires: Overcoming pin limitations in FPGA--based logic emulators. In Duncan A Buell and Kenneth L Pocek, editors, Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, pages 142 -- 151, Los Alamitos, CA, April 1993. IEEE Computer Society Press.

....they frequently require a higher proportion of I O resources vs. logic in each chip than is normally required in single FPGA use. For this reason, some research has focused on methods to allow pins of the FPGAs to be re used for multiple signals. This procedure is referred to as Virtual Wires [Babb93, Agarwal95, Selvidge95], and allows for a flexible trade off between logic and I O within a given multi FPGA system. Signals are multiplexed onto a single wire by using multiple virtual clock cycles, one per multiplexed signal, within a user clock cycle, thus pipelining the communication. In this manner, the I O ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGAbased Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....compared to their direct implementation using bit parallel circuits, our design is 52 times more efficient. Our design is 32 smaller and 38.4 times faster. This comparison strongly backs up our claim in Chapter 2 about the superior efficiency compared to bit parallel circuits. 102 I O D r a[26] r a[25] a[2] in a[1] a[3] a[4] 2 3 1 5 6 8 D r 4 r r r r D D r D 7 D D r a[28] a[8] a[6] a[9] a[7] a[10] a[11] a[27] a[5] a[12] a[13] a[14] a[30] a[15] a[20] a[21] a[20] a[19] a[18] a[16] a[17] a[32] a[33] a[23] out 1 2 3 4 5 6 7 8 9 10 11 12 13 ....

M. Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp.142-151, April 1993.

....data flow graphs. Multiple FPGAs can be used to compute larger problems. The major drawback is the very high complexity of partitioning a design onto multiple FPGAs given a limited amount of pins. Overcoming the pinlimitation in software with design tools is investigated in the Virtual Wires[17] project. Eliminating the pin limitation with multi chip modules of FPGAs is explored in the Teramac project[11] Applications that execute favorably on FPGAs are therefore data intensive applications which can be executed in very deep pipelines (e.g. encryption, pattern matching ,etc. and ....

Jonathan Babb, Russell Tessier, Anant Agarwal, Virtual Wires: Overcoming pin limitations in FPGAbased logic emulators. Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pages 142151, Napa, CA, 1993.

....problem sizes. Multiple FPGAs can be used to compute larger problems. The major drawback is the very high complexity of partitioning a design onto multiple FPGAs given a limited amount of pins. Overcoming the pin limitation in software with design tools is investigated in the Virtual Wires[8] project. Elliminating the pin limitation with multichip modules of FPGAs is explored in the Teramac project[15] Applications that execute favorably on FPGAs are therefore data intensive applications which can be executed in CLB CLB CLB CLB CLB CLB PSM PSM LUT LUT LUT Config. Logic Block ....

Jonathan Babb, Russell Tessier, Anant Agarwal, Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators, Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pages 142-151, Napa, CA, 1993.

....Flexibility A big advantage for a FPMCM is that the solder bumps used for flip chip attachment can be placed over the entire surface of the FPGA, rather than just at the die periphery. See figures 3 and 4. Pin limitations for FPGAs have often been observed to be a limiting factor in FPS [BTA93] In systems where each FPGA is a small part of the total logic and the pattern of interconnections is random, the number of IO needed by an FPGA often increases faster than the square root of the size of the device. This phenomenon is governed by a relationship known as Rent s Rule, which states ....

J. Babb, R. Tessier, and A. Agarwal. Virtual wires: overcoming pin limitations in fpgabased logic emulators. In Proceedings IEEE Workshop on FPGAs for Custom Computing Machines, pages 142--51, 1993.

....for larger problems where significant speedups are possible. The emulator consists of one system control board and 1 to 6 FPGA array boards. We have used 1 FPGA board for our work. Each FPGA board has an array of 64 Xilinx XC4013E FPGA chips. Time multiplexing using the Virtual Wires technique [3] can overcome the pin limitations of the interconnect between chips. The FPGAs run at an internal clock of 20MHz. Since the interconnect is multiplexed between several signals, it can take multiple cycles to transfer the signal between chips. Thus the emulated clock rate is 20MHz divided by number ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators. In Proceedings IEEE Workshop on FPGAbased Custom Computing Machines, pages 142--151, Apr. 1993.

....fewer than ten FPGAs. Partitioning the design across FPGAs is straightforward because of the regular topology used. In our experiments, we have used the partitioning and pin multiplexing techniques in the Ikos SLI logic emulation system originally developed as part of the MIT Virtual Wires effort [2, 7]. This partitioning software can multiplex several inter chip signals to use the same physical pins, thereby circumventing the pin limitations that can often limit the CLB utilization of FPGA designs. Furthermore, the software performs this multiplexing with minimal impact on hardware cycle times. ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators. In Proc. IEEE Workshop on FPGA-based Custom Computing Machines, pages 142--151, Apr. 1993.

....Code generator Asm C Xfig Architecture Description Figure 5: The main stages of the DIL compiler. 1 2 main(fixed 8,0 xin in, fixed 12,0 yout out) 3 4 fixed ,0 x[5] y[5] 5 6 y[0] 0 xin 5; x[0] 1= xin; 7 y[1] y[0] x[0] 4; x[1] 1= x[0] 8 y[2] y[1] x[1] 3; x[2] 1= x[1] 9 y[3] = y[2] x[2] 2; x[3] 1= x[2] 10 y[4] y[3] x[3] 1; x[4] 1= x[3] 11 yout = y[4] 12 P P 0 5 1 1 1 1 2 3 4 1 1 Figure 6: The straight line program and internal graph representation of the FIR filter. program. The result obtained from the FIR filter is shown at the ....

....Xfig Architecture Description Figure 5: The main stages of the DIL compiler. 1 2 main(fixed 8,0 xin in, fixed 12,0 yout out) 3 4 fixed ,0 x[5] y[5] 5 6 y[0] 0 xin 5; x[0] 1= xin; 7 y[1] y[0] x[0] 4; x[1] 1= x[0] 8 y[2] y[1] x[1] 3; x[2] 1= x[1] 9 y[3] y[2] x[2] 2; x[3] 1= x[2] 10 y[4] y[3] x[3] 1; x[4] 1= x[3] 11 yout = y[4] 12 P P 0 5 1 1 1 1 2 3 4 1 1 Figure 6: The straight line program and internal graph representation of the FIR filter. program. The result obtained from the FIR filter is shown at the left of Figure 6. After ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 142--151, Napa, CA, April 1993.

....and the internal organization of each of the FPGA chips. 5. 1 The Processor FPGA Interface With current FPGA densities it is possible to emulate complex logic designs on a single FPGA; however, many of these implementations cannot fully utilize the FPGA gates because there are insufficient I O pins [3]. To overcome this problem, we have designed a memory style interface in which the FPGA chips communicate with the CPU over common address and data busses. Figure 6 shows a block diagram of the interface between the functional units in the FPGA and the CPU. The FPGA is organized as a register file ....

J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," in IEEE Workshop on FPGA-based Custom Computing Machines, 1993.

....FPGA chips are need. 2. The physical hardware size have to be compact and power efficient enough to be of a commercial This work is supported in part by ARPA under ONR Grant N00014 93 1 1334. use. Existing field programmable hardwares are often aimed at system prototyping [13] logic emulation [6][15] experimental applications [1] 2] and lowvolume military applications [4] in which size and power issues were not necessary critical. 3. The programming of the field programmable hardware should be easy enough for the application developers to handle. This requires the support for high level ....

M. Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proc. IEEE Workshop on FPGAs for Custom Computing Machines, pp.142-151, April 1993.

.... pipeline running on an FPGA with a capacity of two pipeline Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Active Cached Cached Cached Active Input i[0] Input i[1] Output o[0] Output o[1] Clock: Stage 1: Stage 2: Stage 3: Stage 4: Stage 5: Figure 1: Pipelined reconfiguration. An example of mapping a five stage pipeline onto a FPGA with the ability to hold two stages. stages. In this example, there are two results produced every five cycles. The FPGA ....

.... FPGA with a capacity of two pipeline Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Cached Cached Cached Cached Active Active Active Cached Cached Cached Active Input i[0] Input i[1] Output o[0] Output o[1] Clock: Stage 1: Stage 2: Stage 3: Stage 4: Stage 5: Figure 1: Pipelined reconfiguration. An example of mapping a five stage pipeline onto a FPGA with the ability to hold two stages. stages. In this example, there are two results produced every five cycles. The FPGA scrolls through the ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal. Virtual wires: Overcoming pin limitations in FPGA-based logic emulators. In D. A. Buell and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 142--151, Napa, CA, April 1993.

....any digital circuit can yield a configuration bitstream, which can then be downloaded onto the FPGA. This results in the FPGA displaying the behavior of the original circuit. This customizable behavior of FPGA a has made them ideal for two applications. The first is emulation of custom chips [2, 3, 4, 5] before they are fabricated. The netlist specifying the circuit of the custom chip is mapped to the FPGA, thus allowing for testing and debugging of the circuit before fabrication. Though one or two orders of magnitude slower than custom hardware, this approach is much faster than software ....

....Progress has been made in all the steps which comprise logic emulation compilation, listed in section 1.2. Techniques for partitioning among FPGAs have been developed using ratio cut [33] and min cut [34, 35] heuristic methods. Simulated annealing [36] has been used for global placement, as in [4]. The problem of FPGA pin limitation has been addressed in by the Virtual Wires project at MIT [37, 4] The approach they take is to time multiplex logical signals between FPGA chips onto the same physical wire. This follows from the observation that for most emulation systems today, circuit ....

[Article contains additional citation context not shown here]

Jonathan Babb, Russell Tessier, and Anant Agarwal. Virtual Wires: Overcoming pin limitations in FPGAbased logic emulators. In Proceedings IEEE Workshop on FPGA-based Custom Computing Machines, pages 142--151, Napa, CA, April 1993. IEEE. Also as MIT/LCS TM-491, January 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pinlimitations in FPGA based logic emulators," Proc. IEEE Workshop on FPGA based Custom Computing Machines, pp. 142-151, Apr. 1993.

....which creates the emulator bitstream. 3.2 Shift Register Architectures We now compare three shift register architectures synthesiz able to Xilinx 4000 FPGAs. Full Shift Register The full shift register architecture was originally proposed as a proof of concept Virtual Wires implementation [7]. This architecture consists of identical input and output shift loops (Figure 17) In output mode, shift loops load emulated signal states at the beginning of each phase and shift these states out serially onto a routed physical connection at the microcycle rate. For connections requiring ....

....x 20ns L x 50ns. Note that to achieve these speeds, FPGAs with the required pin counts must be used to maintain the same critical path and route lengths. It is beyond our partitioning capability to map Sparcle onto 32 pin mesh connected FPGAs without Virtual Wires. However, in our earlier work [7] we did partition a version of Sparcle without memory or external I Os onto 100 pin, 5000 gate FPGAs. We needed at least 31 FPGAs if they were fully connected, and greater than 100 FPGAs if they were connected in a torus. The FPGA explosion is correspondingly worse for the high communication A ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators. In Proceedings 1EEE Workshop on FPGA-based Custom Computing Machines, pages 142 151, Napa, CA, April 1993.

.... mesh and later in a partial crossbar topology [38] Their largest systems use a hierarchical approach to interconnection [37] Thorough reviews of contemporary emulation systems are provided by Hauck [18] and Owen [30] Multiplexing to overcome pin limitations was first proposed by Babb [7] [6] in 1993 and the first successful applications discussed by Tessier [36] Dahl [14] 13] and Hanono [17] Virtual Wires technology has continued to evolve at Virtual Machine Works, Inc. 32] 1] where com mercial emulators based on proprietary VirtualWires(TM) technology are now being produced. ....

J. Babb. Virtual Wires: Overcoming pin limitations in FPGAbased logic emulation. Master's thesis, EECS Deptartment, MIT, Department of Electrical Engineering and Computer Science, February 1994.

....The gate versus IO requirements for partitioned blocks are often mismatched with the gate versus IO balance in commercial FPGAs. Generally, experience has shown that for a given number of gates, partitioned blocks tend to have more IOs than FPGAs do. A compilation technique called VirtualWires [Babb93] attempts to bridge this gap through a multiplexing and pipelining approach that enables superfluous gates on FPGAs to be traded for pins, thus allowing more efficient use of FPGA resources. The basic idea is that when the number of logical signals that must cross partitioned boundaries is ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....chip boundaries. Current emulators only use a fraction of potential communication bandwidth because they dedicate each FPGA pin (physical wire) to a single emulated signal (logical wire) These logical wires are not active simultaneously and are switched at emulation clock speeds. Virtual wires [3] overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency of the FPGA. A virtual wire represents a connection from a logical output onone FPGA to a logical input on another FPGA ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators In IEEE Workshopon FPGAs for Custom Computing Machines, Napa, California, April 1993.

....DISTRIBUTE January 18, 1994 2 Global Placer Route Embedder Global router phase assign. Partitioned Netlist Static Timing Analyzer Virtual Wires Communication Network Figure 1: Virtual Wires Software Compiler Kernel 1 Introduction Introduced at last year s IEEE FPGA Workshop, Virtual Wires [4] overcome the pincount limitation that restricts the efficiency of current FPGA based logic emulators. Existing systems dedicate each FPGA pin to a single emulated signal, rapidly consuming pins and limiting utilization of available FPGA gates to typically 10 to 20 percent. Virtual Wires ....

....research. 2 The Wire Virtualizer Kernel The core of the Virtual Wires compiler is a set of software modules that read a partitioned netlist and produce an inter partition communication network using Virtual Wires (Figure 1) The initial stages of this process have been discussed previously [3] [4]. Here we summarize these steps, then concentrate on the communication circuitry produced by the compiler. DRAFT DO NOT DISTRIBUTE January 18, 1994 3 2.1 Static Timing Analysis In order to schedule the mapping of physical wires between partitions onto virtual wires, a timing ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings, IEEE Workshop on FPGA-based Custom Computing Machines,pages 142--151, Napa, CA, April 1993. IEEE. Also as MIT/LCS TM-491, January 1993.

....research. 2 The Wire Virtualizer Kernel The core of the Virtual Wires compiler is a set of software modules that read a partitioned netlist and produce an inter partition communication network using Virtual Wires (Figure 1) The initial stages of this process have been discussed previously [3] [4] Here we summarize these steps, then concentrate on the communication circuitry produced by the compiler. DRAFT DO NOT DISTRIBUTE January 18, 1994 3 2.1 Static Timing Analysis In order to schedule the mapping of physical wires between partitions onto virtual wires, a timing ....

J. Babb. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. Master's thesis, EECS Department, MIT, Nov. 1993.

....of a sequencer and shift loops. The sequencer is a distributed finite state machine, establishing virtual connections between FPGAs by strobing logical wires into special shift registers. These registers are then alternately connected to physical wires according to the predetermined schedule. See [1] for a more detailed description. Emulation The emulation clock of the logic design is divided into multiple evaluation phases because combinational logic between flip flops of the emulated design may be split across multiple partitions. Evaluation from logical inputs takes place at the ....

J. Babb, R. Tessier, and A. Agarwal. Virtual wires: Overcoming pin limitations in fpga-based logic emulators. In Proc. of the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1993.

....memory system model; rather it builds a user configurable instruction set on top of fixed, core instruction set, and synthesizes a user configurable system model on top of primitive, commodity, hardware elements such as DRAM and FPGAs. This work leverages our previous FPGA work, Virtual Wires [1], in conjunction with behavioral compilation technology, to view an array of FPGAs as a machine independent computing fabric. The RAW machine comprises very simple commodity hardware including SRAMs, DRAMs, a large amount of primitive programmable logic in the form of FieldProgrammable Gate Arrays ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators. In Proceedings IEEE Workshop on FPGA-based Custom Computing Machines, pages 142--151, Napa, CA, April 1993. IEEE. Also as MIT/LCS TM-491, January 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, CA, 1993, pp. 142-151.

No context found.

Jonathan Babb, Russell Tessier, and Anant Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In IEEE Workshop on FPGAs for Custom Computing Machines (FCCM '93), pages 142--151, Napa Valley, California, April 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," presented at the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," in Proc. IEEE Workshop on FPGA's for Custom Computing Machines, Apr. 1993.

No context found.

M. Dahl, J. Babb, R. Tessier, S. Hanono, D. Hoki, and A. Agarwal. Virtual wires: Overcoming pin limitations in fpga-based logic emulators. In IEEE Workshop on FPGAs for Custom Computing Machines, pages 142--151, 1993.

No context found.

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", FCCM, pp. 142-151, 1993.

No context found.

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

No context found.

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

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