J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, CA, 1993, pp. 142-151.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....used in emulators. Atypical emulation board consists of several FPGAs interconnected to 3 10 6 Cost ( Performance (Hz) COST PERFORMANCE Software Simulator (VCS, Modelsim) 10K 0.5M Our Approach Emulator (Axis, Tharas) ###### ## ###### ### ########## ### ########## gether. [3, 4] demonstrated the Virtual Wires scheme to time multiplex wires on physical pins connecting the FPGAs, thereby improving their utilization. However, such large emulation systems are neither cost e ectivenor scalable. Several emulation vendors use multiple FPGAs and specially designed hardware ....

J. Babb,R.Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In ########### ## ### #### ######## ## ##### ### ###### ######### ########,April 1993.

.... of such systems include the experimental DECPeRLe board [18] SPLASH 2 [8] Teramac [19] and the commercial WILD series from Annapolis Microsystems [20] Some software tools exist which can automatically partition the design between multiple FPGAs on a board using higher level abstractions [21]. For a detailed overview of FPGA devices and multi FPGA architectures see [5] SPLASH SPLASH and SPLASH 2 [8] its successor, can be conceptually viewed as a system of linear array of processing elements. This architecture makes SPLASH 2 a good candidate for systolic applications with limited ....

R. Tessier J. Babb and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," IEEE Workshop on FPGAs for Custom Computing Machines, April 1993.

....shortest path for routing a net, breadth first search is performed starting from the source FPGA and stopping once the target FPGA is reached. The TIERS algorithm also identifies critical nets and gives them higher priority to achieve as much as a factor of 2. 5 speed improvement over prior work [Babb93]. A different approach towards topology independent routing is adopted in [Kim96] For each topology, all possible routing paths (patterns) between every pair of FPGAs are stored. To minimize inter FPGA routing delays, only paths of length one or two hops are considered. When routing each net, ....

J. Babb et al, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....they frequently require a higher proportion of I O resources vs. logic in each chip than is normally required in singleFPGA use. For this reason, some research has focused on methods to allow pins of the FPGAs to be re used for multiple signals. This procedure is referred to as Virtual Wires [Babb93, Agarwal95, Selvidge95], and allows for a flexible trade off between logic and I O within a given multi FPGA system. Signals are multiplexed onto a single wire by using multiple virtual clock cycles, one per multiplexed signal, within a user clock cycle, thus pipelining the communication. In this manner, the I O ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....the North South axis. Given the regimen of two clock cycles per incoming pixel, communication can be duplexed. Hence, 86 bits can be communicated by multiplexing the outputs and inputs on these North South 43 pin connections. This approach is similar to the method used in the Virtual Wires machine [Babb93]. This multiplexing will be simplified by the Xilinx EX chips with their strobed I O registers and multiplexed I O pins. 4.3 Memory use A census transform requires several scanlines of data in order to form the census vector for a pixel in one cycle. The computation needs access to several pixels ....

J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, IEEE FPGAs for Custom Computing Engines, pp. 142-151, April 1993.

....as an extension of the physical FPGA device: the applications have a virtual view of the FPGA that is mapped on the available physical device by the operating system, in a way similar to virtual memory. In other words, the FPGA is virtualized by multiplexing its physical components. The same idea [9] has also been followed for increasing the number of FPGA I O pins, leading to the concept of virtual wires. In both cases the goal is to extend the capabilities of the FPGA devices. Physical Virtual layer Layer Fig. 1. Physical layer and Virtual layer: A virtual configurable logic block is ....

J. Babb, R. Tessier, A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines'93, 1993.

.... of such systems include the experimental DECPeRLe board [76] SPLASH 2 [19] and Teramac [1] and the commercial WILD series from Annapolis Microsystems [56] Some software tools exist which can automatically partition the design between multiple FPGAs on a board using higher level abstractions [42]. For a detailed overview of FPGA devices and multi FPGA architectures see [40] 21 2.2.1 SPLASH SPLASH and SPLASH 2 [19] its successor, can be conceptually viewed as a system of linear array of processing elements. This architecture makes SPLASH 2 a good candidate for systolic applications ....

R. T. J. Babb and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. IEEE Workshop on FPGAs for Custom Computing Machines, April 1993.

....as an extension of the physical FPGA device: the applications have a virtual view of the FPGA that is mapped on the available physical device by the operating system, in a way similar to virtual memory. In other words, the FPGA is virtualized by multiplexing its physical components. The same idea [10] has also been followed for increasing the number of FPGA I O pins, leading to the concept of virtual wires. In both cases the goal is to extend the capabilities of the FPGA devices. As opposed, we see a virtual FPGA as a simplified version of a physical FPGA. The idea is not to enhance the FPGA ....

J. Babb, R. Tessier, A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines'93, 1993.

....that he leveraged this filtering capability to display disassembled versions of programs as they executed on a processor implemented on Teramac; this was, of course, much easier than observing and deciphering the machine code that the processor executed. InnerView As a part of the Virtual Wires[29] logic emulation project, Silvina Hanono created the InnerView Hardware Debugger[30] for the Virtual Wires emulation board. The debugger had two significant features. First, the debugger leveraged the configuration readback capability of the Xilinx FPGAs in the Virtual Wires emulation system to ....

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators", in Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, D. A. Buell and K. L. Pocek, Eds., Napa, CA, Apr. 1993, pp. 142--151.

....the NorthSouth axis. Given the regimen of two clock cycles per incoming pixel, communication can be duplexed. Hence, 86 bits can be communicated by multiplexing the outputs and inputs on these North South 43 pin connections. This approach is similar to the method used in the Virtual Wires engines [Babb93]. This multiplexing will be simplified by the Xilinx EX chips with their strobed I O registers and multiplexed I O pins. 4.3 Memory use A census transform requires several scanlines of data in order to form the census vector for a pixel in one cycle. The computation needs access to several ....

J. Babb, R. Tessier, and A. Agarwal, Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators, IEEE FPGAs for Custom Computing Engines, pp. 142-151, April 1993.

....inserted to handle some of the logic. If too many signals need to be routed along a given link, an extender card spanning several daughter card positions can be added, with new routing paths included on the inserted card. Note that while most routing limitations can be dealt with by Virtual Wires [Babb93], a method for multiplexing several circuit wires onto one physical connection, added cards for routing will reduce the reliance on Virtual Wires, thus decreasing both area and cycle time. For signals that must go long Device Device Device FPGA Device FPGA Daughter Card Device FPGA ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

....packaging technology in its growth. Although the FPGA s can be clocked very fast (50 100 MHz) a hardware emulator usually runs very slowly (a few megahertz) because, during every emulation cycle, signals must travel through combinational paths across multiple FPGA s. Virtual wire technology [2], 5] 11] takes advantage of the high FPGA speed, with respect to the low emulation speed. By means of time division multiplexing (TDM) it uses each physical inter FPGA wire to transport several logical signals during each emulation cycle. In a virtual wire based emulator, an emulation cycle ....

....can easily have a logic capacity of more than 10 000 gates. However, the number of I O pins is restricted to a few hundred. For example, the largest chip from Xilinx (XC4025) 19] has 25 000 gates housed in a 299 pin package, of which only 256 are signal pins. III. VIRTUAL WIRING Babb et al. [2], 5] 11] proposed using a TDM scheme to increase the effective inter FPGA communication capability during hardware emulation. We use Fig. 2 to illustrate the operation principle of virtual wiring. Suppose the emulator is to run at 1 MHz, and the longest combinational path travels across six ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," in Proc. IEEE Workshop FPGA-Based Custom Computing Machines, Napa, CA, Apr. 1993, pp. 142--151.

.... hardware platform much simpler, smaller, and cheaper than an emulator, where inter FPGA communications is a complex problem requiring expensive solutions, such as hierarchical crossbar structures [33] or dedicated field programmable interconnect chips [23] or time multiplexing hardware [6]. Unlike multi FPGA partitioning techniques which have to deal with a specific board interconnect scheme, our decomposition is independent of the architecture of the target hardware platform. The lack of any inter FPGA interconnect also provides the basis for the virtual hardware mechanism: if we ....

J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGAbased Logic Emulators," Proc. Symp. on Field-Programmable Custom Computing Machines, pp. 142-151, April 1993

....of I O pins that enable data communication between two connected computing resources. Sharing ports among several channels defuses the problem of limited I O pin resources. Port sharing applies to external edges of the node types b and c and has been extensively used in the Virtual Wire project [2, 1]. We extend port sharing to time exclusive configurations of runtime reconfigurable systems. Therefore, we di#erentiate between two types of port sharing: Intraconfiguration port sharing allows communication channels in the same configuration to share I O ports by adding multiplexing and ....

....configurations of runtime reconfigurable systems. Therefore, we di#erentiate between two types of port sharing: Intraconfiguration port sharing allows communication channels in the same configuration to share I O ports by adding multiplexing and demultiplexing interface circuitry [1]. This technique can be applied to both CTR and RTR systems. Interconfiguration port sharing allows communication channels in di#erent configurations of one FPGA to share I O ports. These channels would otherwise be mapped to di#erent ports as configurations of other FPGAs could require that ....

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In IEEE Workshop on FPGA-based Custom Computing Machines, pages 142--151, Napa, CA, April 1993.

....Clos like X 12 XC3xxx bus Table 2.1: Partial list of emulators and prototyping boards describing interconnection architecture and chips supported. Some of the boards listed in the table use what we call pure interconnect structures, for example PeRLe0 [11] PeRLe1 [11] and Virtual Wires [16] all use a mesh architecture to implement the interconnection among FPGAs while the X 12 [17] of National Technologies Inc. uses a bus. The Anyboard [10] and Splash 1 [13] use a linear array. BORG [5] and ACME consist of user FPGAs connected together via a Clos like network, also implemented with ....

....the logic level (always referring to time) But this technique does not really help us for ACME, since the neurons are designed to process data in serial fashion. Time multiplexing is used as a means to reduce the number of pins required to implement a system and is used by Virtual Wires of MIT [16]. A specialized program has to insert extraneous logic at the edge of the user defined logic to enable the multiplexing and de multiplexing of signals (a chain of shift registers) The disadvantages of this implementation are that debugging with an oscilloscope is rendered almost impossible, and ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142--151, April 1993.

....for routing channels as implemented on a FPGA. The structures that occupy large area on FPGAs are reduced to a bare minimum using SRAM technology. Second, since the circuit evaluation is time multiplexed, it makes sense to time multiplex the interconnect as well. In the VirtualWires TM system [BTA93] [SADB95] small shift loops are added to the circuitry of partitions mapped into a FPGA based logic emulator. Each shift loop shifts the results of computations on one FPGA onto a wire bound for another FPGA where another loop of the same length demultiplexes the signals. The shift loops have a ....

J. Babb, R. Tessier and A. Agarwal. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators," Proc. FPGAs for Custom Computing Machines, 1993, pp. 142-151.

....and variable board architectures, software techniques are used to make the design board independent. It becomes the partitioner and the synthesis tools responsibility to adapt the design to the RC architecture utilized. Several mechanisms exist to reuse pins for several connections; Virtual wires [12] offer a way of overcoming pin limitations in FPGAs by statically scheduling data transfers so that multiple transfers re use the same set of pins. This comes at the price of statically scheduling accesses. On the other hand, Vahid used functional partitioning and the concepts of FunctionBus ....

J. Babb, R. Tessier, A. Agarwal. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators". In Proceedings of FPGAs for Custom Computing Machines, 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pinlimitations in FPGA based logic emulators," Proc. IEEE Workshop on FPGA based Custom Computing Machines, pp. 142-151, Apr. 1993.

....which creates the emulator bitstream. 3.2 Shift Register Architectures We now compare three shift register architectures synthesiz able to Xilinx 4000 FPGAs. Full Shift Register The full shift register architecture was originally proposed as a proof of concept Virtual Wires implementation [7]. This architecture consists of identical input and output shift loops (Figure 17) In output mode, shift loops load emulated signal states at the beginning of each phase and shift these states out serially onto a routed physical connection at the microcycle rate. For connections requiring ....

....x 20ns L x 50ns. Note that to achieve these speeds, FPGAs with the required pin counts must be used to maintain the same critical path and route lengths. It is beyond our partitioning capability to map Sparcle onto 32 pin mesh connected FPGAs without Virtual Wires. However, in our earlier work [7] we did partition a version of Sparcle without memory or external I Os onto 100 pin, 5000 gate FPGAs. We needed at least 31 FPGAs if they were fully connected, and greater than 100 FPGAs if they were connected in a torus. The FPGA explosion is correspondingly worse for the high communication A ....

[Article contains additional citation context not shown here]

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming pin limitations in FPGA-based logic emulators. In Proceedings 1EEE Workshop on FPGA-based Custom Computing Machines, pages 142 151, Napa, CA, April 1993.

.... mesh and later in a partial crossbar topology [38] Their largest systems use a hierarchical approach to interconnection [37] Thorough reviews of contemporary emulation systems are provided by Hauck [18] and Owen [30] Multiplexing to overcome pin limitations was first proposed by Babb [7] [6] in 1993 and the first successful applications discussed by Tessier [36] Dahl [14] 13] and Hanono [17] Virtual Wires technology has continued to evolve at Virtual Machine Works, Inc. 32] 1] where com mercial emulators based on proprietary VirtualWires(TM) technology are now being produced. ....

J. Babb. Virtual Wires: Overcoming pin limitations in FPGAbased logic emulation. Master's thesis, EECS Deptartment, MIT, Department of Electrical Engineering and Computer Science, February 1994.

....The gate versus IO requirements for partitioned blocks are often mismatched with the gate versus IO balance in commercial FPGAs. Generally, experience has shown that for a given number of gates, partitioned blocks tend to have more IOs than FPGAs do. A compilation technique called VirtualWires [Babb93] attempts to bridge this gap through a multiplexing and pipelining approach that enables superfluous gates on FPGAs to be traded for pins, thus allowing more efficient use of FPGA resources. The basic idea is that when the number of logical signals that must cross partitioned boundaries is ....

J. Babb, R. Tessier, A. Agarwal, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 142-151, 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, Los Alamitos, CA, 1993, pp. 142-151.

No context found.

Jonathan Babb, Russell Tessier, and Anant Agarwal. Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators. In IEEE Workshop on FPGAs for Custom Computing Machines (FCCM '93), pages 142--151, Napa Valley, California, April 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," presented at the IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1993.

No context found.

J. Babb, R. Tessier, and A. Agarwal, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulators," in Proc. IEEE Workshop on FPGA's for Custom Computing Machines, Apr. 1993.

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