J. K. Bennet, J. B. Carter, andW.Zwaenepoel. `Adaptive Software CacheManagement for Distributed Shared Memory Architectures'. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 125--134, June 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....program can of course be written with sensitivity to the underlying hierarchy [CGM91, CGHM93] The basic unit of allocation in the SRAM main memory is a page. This paper leaves open the question of coherency and multiprocessor implementation; strategies from distributed shared memory could apply [BCZ90] Page translation in RAMpage is done using an inverted page table, a page table indexed on the physical instead of the virtual address [HH93] for several reasons: # the SRAM main memory is relatively small, and an inverted page table is well suited to small physical memories (since otherwise ....

J.K. Bennet, J.B. Carter, and W. Zwaenepoel. Adaptive software cachemanagement for distributed shared memory architectures. In Proc. 17th Int. Symp. on Computer Architecture (ISCA '90), pages 125--134, Seattle, WA, May 1990.

....have already been introduced. Write pipelining has been proposed to reduce update delays[10] Lazy invalidation policies have been investigated[9] Attempts have also been made to use knowledge about how data objects are manipulated to customize the manner in which consistency is enforced[3]. Most approaches assume that conveying written data to memory and carrying out any associated consistency activity are an indivisible unit. Often called a write perform . This paper examines the benefits of decoupling the memory update process from the dissemination of invalidations. ....

J.K. Bennet, J.B. Carter, and W. Zwaenepoel. Adaptive software cache management for distributed shared memory architectures. In 17th International Symposium on Computer Architecture, pages 125--134, June 1990.

....from other environments, see, for example, the figures presented in [Levelt et al. 92] An alternative to object mobility is thread migration i.e. function shipping instead of data shipping. Actually, both object and thread mobility have proved their value in practical implementations [Bennett et al. 90, Chase et al. 92b, Dasgupta et al. 91, Garrett et al. 92, Jul et al. 88] A programmer may explicitly migrate a thread to a target host, but typically migration is triggered by page faults as described above. Note that in PANDA thread migration is not subject to false sharing. Furthermore, ....

J.K. Bennet, J.B. Carter, W. Zwaenepoel. Adaptive Software Cache Management for Distributed Shared Memory Architecture. Proc. 17th Annual Int. Symposium on Computer Architecture, Seattle, Washington, pp. 125-134, May 1990.

....of a single coherence strategy, it provides a suite of different coherence mechanisms. It uses program annotations to match a particular consistency protocol to a particular data object. Munin classifies data objects according to their access pattern and uses a type specific coherence scheme [21] depending on the type of the shared data object. The objects supported are: read only, migratory, producer consumer, reduction, concurrent write shared and result objects. There are also provisions to incorporate additional objects. The authors motivation for the mixed protocol approach is the ....

J. K. Bennet, J. B. Carter, andW.Zwaenepoel. `Adaptive Software CacheManagement for Distributed Shared Memory Architectures'. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 125--134, June 1990.

....code on a RAMpage versus a conventional cached machine. Multiprocessor systems introduce another range of problems. To minimize variables in this initial research, multiprocessor systems are not considered. However, some lessons could be drawn from work on distributed shared memory (DSM) systems [3, 11]. 5.4 Final Summary Overall, the RAMpage approach appears to be promising. Further work is needed to investigate missing details. However, given initial data presented in this paper, there is reason to continue with further investigation. The fact that an improvement of up to 25 was seen over ....

J.K. Bennet, J.B. Carter, and W. Zwaenepoel. Adaptive software cache management for distributed shared memory architectures. In Proceedings of the 17th International Symposium on Computer Architecture, pages 125--134, Seattle, WA, May 1990.

....of the different hardware cache coherent protocols [EK88] Weber and Gupta [WG89] divide the different types of sharing into 6 categories: read only, migratory, synchronization, read mostly, and concurrent read write sharing. This is extended further by Bennet, Carter and Zwaenepoel in [BCZ90b, BCZ90a] who add producer consumer and result types to the list. The reason for the differences are that Weber and Gupta are looking CHAPTER 2. RELATED WORK 11 at cache coherent hardware, while Bennet, Carter and Zwaenepoel have distributed shared memory in mind. However, the final results can be ....

John K. Bennet, John B. Carter, and Willy Zwaenepoel. Adaptive software cache management for distributed shared memory architectures. In SIGARCH, pages 125--134, 1990.

....code on a RAMpage versus a conventional cached machine. Multiprocessor systems introduce another range of problems. To minimize variables in this initial research, multiprocessor systems are not considered. However, some lessons could be drawn from work on distributed shared memory (DSM) systems [BCZ90, DKCZ93] 6.4 Final Summary Overall, the RAMpage approach appears to be promising. Further work is needed to investigate missing details. However, given initial data presented in this paper, there is reason to continue with further investigation. The fact that an improvement of up to 25 was seen ....

J.K. Bennet, J.B. Carter, and W. Zwaenepoel. Adaptive software cache management for distributed shared memory architectures. In Proceedings of the 17th International Symposium on Computer Architecture, pages 125--134, Seattle, WA, May 1990.

....Alewife project differs somewhat from the other research architectures surveyed in this section, in that it consists of a mesh topology network of memory and processor nodes. In other words, it is not hierarchical. In some respects, it is closer in philosophy to distributed shared memory systems [Bennet et al. 1990]: the network latency is high enough to justify techniques such as a partially software based cache miss handler, and context switching on cache misses [Agarwal et al. 1990] The actual cost of a miss depends on how far away the required block is found. On an 8000 processor system, the average ....

JK Bennet, JB Carter and W Zwaenepoel. Adaptive Software Cache Management for Distributed Shared Memory Architectures, Proc. 17th Int. Symp. on Computer Architecture, Seattle, WA, May 1990, pp 125--134.

No context found.

J. K. Bennet, J. B. Carter, andW.Zwaenepoel. `Adaptive Software CacheManagement for Distributed Shared Memory Architectures'. In Proceedings of the 17th Annual International Symposium on Computer Architecture, pages 125--134, June 1990.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC