Steven L. Scott, "Toward the Design of Large-Scale, Shared-Memory Multiprocessors. " Ph.D. Thesis, University of Wisconsin-Madison, August 1992. Home/Search Document Details and Download
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Identification And Optimization Of Sharing Patterns For Scalable.. - Kaxiras (1998) (4 citations) (Correct)
....does depend on the network topology, the size of the system, and the congestion characteristics of the network. Scott discusses the scalability of latency in his thesis and argues that asymptotically latency must increase as at least O(N 1 2 ) where N is the number of nodes in the system [86]. Since the aforementioned protocols do not take into account network locality their tree structure maps arbitrarily on top of the network topology the latency of their writes is worse than logarithmic. Furthermore, these protocols actually increase traffic in the network over non tree based ....
....directories pay a severe penalty whenever the pointer capacity is exceeded. GLOW provides a solution to this situation by providing dynamic pointers, making solutions such as dynamic pointer allocation [90] unnecessary. 3.7. 3 GLOW and pruning caches Pruning caches, proposed by Scott and Goodman [88,86] are hierarchical directories based on the multilevel inclusion property. Pruning caches allow a directory entry in a sharing tree to be replaced without invalidating its subtrees. However, for any subsequent operation (e.g. invalidation) the conservative assumption must be made that the subtrees ....
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Steven L. Scott, "Toward the Design of Large-Scale, Shared-Memory Multiprocessors. " Ph.D. Thesis, University of Wisconsin-Madison, August 1992.
Performance Analysis Of Multiprocessor Interconnection Networks.. - Turner (1995) (Correct)
....all HOL packets (regardless of conflicts) into their output queues in a single cycle [12, 29] This can be achieved by using a switch implementation that runs N times as fast as the links between switches. The former is impractical, considering the current technique of using pipelined channels [30] to maintain multiple bits on the fly in a wire. Pipelined channel techniques mean that speed of light and distance limitations no longer need to restrict the clock rate of inter switch links, only transmission line effects need do so. Since modern cables and circuit board traces are capable of ....
S. L. Scott, Toward the Design of Large-Scale Shared-Memory Multiprocessors. PhD thesis, University of Wisconsin - Madison, 1992.
Request Combining in Multiprocessors with Arbitrary.. - Lebeck, Sohi (1994) (7 citations) (Correct)
....the same as the technique used in the Ultracomputer. An interesting example of IIC read combining can be found in schemes with hierarchical cache memory structures, such as Cache Only Memory Architecture (COMA) machines [7, 27] or Non Uniform Memory Access (NUMA) machines with hierarchical caches [18, 23, 30]. Here read combining can be implemented by using a technique similar to the CHoPP method of read combining. A read miss of a cache block at one level of the hierarchy causes a request to be propagated to the next higher level in the hierarchy. Subsequent read misses of the same cache block at the ....
Scott, S. L., "Toward the Design of Large-Scale Shared-Memory Multiprocessors," Ph. D. Thesis, Department of Computer Science (Technical Report #1100), University of Wisconsin-Madison, Madison, WI 53706, July 1992.
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