Andrew S. Tanenbaum. Structured Computer Organization, chapter 2. PrenticeHall, Inc., fourth edition, 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....access time, low energy consumption, high bandwidth and low cost. However, this is not possible as technologies with, for example low access times, tend to be more expensive than those with high access times. The solution to this problem is the organisation of these memories in a memory hierarchy [44]. An illustration of the memory hierarchy is provided in Figure 2.1. As the hierarchy is descended, access times and energy consumption for accesses increase, and cost decrease, providing for greater capacities. Compilers, operating systems and hardware provide an abstraction of the memory ....

....Cache Secondary storage Figure 2.1: The memory hierarchy The memory hierarchy is intended to provide memory of the capacity and the cost of the lowest level with the access time, energy consumption and throughput of the highest level. This is achievable as a result of the principle of locality [44]. Memory accesses tend to exhibit two types of locality. An access to a memory location is likely to be followed by an access to a nearby memory location this is known as spatial locality. Also, a memory access is likely to be to a recently accessed memory location this is known as ....

Andrew S. Tanenbaum. Structured Computer Organization, chapter 2. PrenticeHall, Inc., fourth edition, 1999.

....to write and execute many algorithms (assembly programs) and to visualize the execution and the results in objects like: registers, stacks, arrays represented in components of C Builder 5.0, used to construct and compile the simulator. It is also possible to study the functioning of CISC [10] [12] network processor, write routing algorithms and offer to developers the possibility to write compilers for a virtual network processor (this simulator) like a virtual machine. The learning possibilities of this tool are described in Learning Tool Usability topic. The user interface has one main ....

....like: to transmit, to receive, and some data operations in many registers and memory without changing the window. There is a relationship between windows and modules, from the right to the left. This relation can explain the functioning of packet processing and the hierarchical memory [10] [12] (buffers, registers and memory) This option helps to visualize the performance speed from hierarchic. Functioning: Firstly the packet is constructed (Input Packets Module) in any place of network, and arrives in processor through a serial input, represented by temporary buffers. From temporary ....

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Tanenbaum, Andrew S.; Goodman, James R., Structured Computer Organization, Prentice-Hall, 1999

....world. In the case of this processor, the components of the house that is electronically controlled are: gates, windows, doors, illumination, sound devices and appliances. After the design stage of the KMT microprocessor architecture, where the students looked to study every theory seen in class [14] and in several bibliographies that treat the subject, it came to the verification stage through functional simulation. We defined the C language with Borland C Builder 4.0 compiler as tool for software coding. Thus, we could obtain a better maintenance and possible evolutions for more ....

Tanenbaum, Andrew S, "Structured Computer Organization", 4 th ed., Prentice-Hall, 1999.

....likely to perform well in their courses. By illustrating the flow of data within a CPU as it fetches, decodes, and executes instructions, this simulator will help students to learn the material better. Most textbooks for computer organization and architecture have some type of simulator available [1 3]. One notable exception [4] does not offer a simulator. However, these simulators only accept program input and output results, such as the contents of regis ters after each instruction. They show students what happens within a computer, but not the actions that cause each operation to occur. ....

Tanenbaum, A. Structured Computer Organization, 4th edition, Upper Saddle River, NJ: Prentice Hall, 1999.

....Computer activities teach students the basic architecture principles underlying the operation of a modern digital computer using components commonly found in their own personal computers. We base our activities on two simple computer models adapted from introductory computer engineering texts [5] [6]. Less complicated activities use a single tier bus architecture model shown in Figure 1. More complicated activities for higher grade students use the two tier bus architecture shown in Figure 2. For specific activities some components, such as Cache Memory, may be omitted from the model and ....

Tanenbaum, A., Structured Computer Organization, Prentice Hall, 1999.

....use to achieve that goal. When designing simulation software, we concentrate on the visual aspects of the simulation. Consider, for example, the topics taught in a course on computer architecture. Most textbooks for computer organization and architecture have some type of simulator available [1] [3]. One notable exception [4] does not offer a simulator. However, these simulators only accept program input and output results, such as the contents of registers after each instruction. They show students what happens within a computer, but not the actions that cause each operation to occur. ....

Tanenbaum, A. Structured Computer Organization, 4th edition, Upper Saddle River, NJ: Prentice Hall, 1999.

....For the purposes of this paper it is convenient to work in terms of a idealized entity that we will call an abstract Java machine (AJM) The singu lar property of this machine is that it will execute a Java program. This notion of a (language, machine) pair goes back at least as far as Tanenbaum [3]. It allows us to describe the semantics of the lan guage by providing an informal operational semantics of the machine, in terms of data structures dynamically created inside the machine and in terms of transformations on those structures. Techniques that make this notion of language semantics ....

Andrew S. Tanenbaum, Structured Computer Organi- zation, Prentice Hall, 1976.

....Computer Architecture concepts are usually analyzed theoretically, leaving the students with incomplete and sometime erroneous views of how a computer works. These misconceptions remain in higher level courses making difficult a thorough learning in the area. Computer organization literature [1, 2, 3, 4, 5] usually attacks the complexity of computer systems by using several layers to describe them. Each layer describes one abstraction level, providing higher insight when analyzing a given subsystem. These levels usually include assembly language, instruction sets, microprogramming and digital logic. ....

TANENBAUM, A. "Structured Computer Organization", 4 th edition, Prentice Hall, New Jersey, 1999.

....for Java requires an extensive working knowledge about its virtual machine organization and functionality. Java virtual machine (JVM) instruction set architecture (ISA) defines categories of operations that manipulate several data types, reached through a well defined set of addressing modes [25,26,27,28,29]. JVM specification defines the instruction encoding mechanism required to package this information into the bytecode stream. It also includes details about the different modules required for processing these bytecodes. At runtime, the JVM implementation and the execution environment affect the ....

A. Tanenbaum and J. Goodman, Structured Computer Organization, Fourth Edition, Prentice Hall, Englewood Cliffs, NJ, 1999.

....implementation of hardware components by using simulation. 1. Introduction The theoretical study of computer architecture and organization usually give the students an incomplete and sometime erroneous view of how a computer system works. Computer organization bibliography (for instance, [1, 2, 3]) usually emphasizes the basic behavior of a computer system. The lack of practical experience can make the underlying complexity of the subsystems and their interaction not to be completely understood. The main problems are related with the existence of several layers to be studied. The ....

....figure shows the implementation of the transition functions using the tool. Model IncDec: externalFunction( const ExternalMessage msg ) switch (msg.port( When x is received in the port y; case OP0: OP[0] int) msg.value( case OP1: OP[1] int) msg.value( case OP2: OP[2] = int) msg.value( case OP3: OP[3] int) msg.value( case OP4: OP[4] int) msg.value( case FCOD: FCOD = int) msg.value( if( FCOD = 1 ) increment RES[0] OP[0] 16 OP[1] 8 OP[2] 4 OP[3] 2 OP[4] 1) 32; else decrement RES[0] OP[0] 16 OP[1] 8 OP[2] 4 ....

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Tanenbaum, A., Structured Computer Organization, 3 rd edition, Prentice Hall, New Jersey, 1990.

....distribution of the clock pulse but also of data. Note: no technology will be able to exceed the physical limit of the speed of light (29:9cm=ns) The interconnect and the dielectric material will a ect the propagation delay (for example the speed of a signal in copper is approximately 20cm=ns [Tan90] The clock signal is designed to make the whole system operate together in synchronization. This forces the whole system to be switching at the clock frequency which concentrates radiation at this xed frequency (and its multiples) which leads to problems with electro magnetic compatibility ....

....critical sections and mutual exclusion implement a blocking type of communication, i.e. when one process is accessing the exclusive area or code, then the other process can be forced to wait, so its access is blocked, see Figure 2.2. The idea that hardware and software are logically equivalent [Tan90] implies that an algorithm implemented using software can also be implemented in hardware if required. In this case the equivalent of a critical section in software is called mutual exclusion if implemented in hardware, and both can perform the same logical function. The choice of implementation ....

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A.S. Tanenbaum. Structured computer organization. Prentice Hall, 1990. pp47-48.

....discuss the structure of the hardware system components: memory, processors, I O devices, and control processor. Our assumption here is that the reader is aware of the structure of a computer from a computer organization book. There are many good introductory texts for this part. Some of them are [5, 6, 40, 96]. However, no one of these texts treats the components of a hardware systems as systems. We consider the hardware system components as subsystems of the hardware system and specify them as data types. The operations of these data types are the actions of the hardware system components that achieve ....

A.S. Tanenbaum. Structured Computer Organization. Prentice-Hall, 1990.

....runs as C processes, in such a way that the processes, as a whole, maintain the functionality of P , yet execute as separate communicating processes. The value of C is chosen by the restructuring engineer. It must be at least 2. We use the term process to refer to a program in execution [71], and we refer to the collection of source code that will give rise to a process as a cluster . P consists of a set of global variables, V , and a set of functions, F . We use the word function in the generic sense of a named sequence of statements. We further assume that 6 Figure 1.5 A simple ....

Andrew S. Tanenbaum. Structured Computer Organization. Prentice-Hall, second edition, 1984. (cited on page 5)

.... the operating system, it must be possible to resume the program at the instruction which caused the problem (preciseness) Furthermore, interrupt handlers must be able to call or interrupt each other (nesting) because a slow device could otherwise block a faster device longer than tolerable [47, 49]. Such an interrupt mechanism requires both, hardware support and a software protocol to be obeyed, and therefore, it is acknowledged to be a particularly hard part of machine design ( 19] p. 214) Even most recent publications on interrupt handling [19, 45, 47, 49, 52, 54, 55] sketch only parts ....

....a faster device longer than tolerable [47, 49] Such an interrupt mechanism requires both, hardware support and a software protocol to be obeyed, and therefore, it is acknowledged to be a particularly hard part of machine design ( 19] p. 214) Even most recent publications on interrupt handling [19, 45, 47, 49, 52, 54, 55] sketch only parts of those mechanisms. Usually, they ignore the interactions of the software protocol and the hardware support, or restrict the solutions to the sequential processing of interrupts. With the notable exception of [25] no attempt is made to prove the correctness of an interrupt ....

A.S. Tanenbaum. Structured Computer Organization. Prentice-Hall International, Inc., 1990.

....San Antonio, TX 78249 1 Introduction The University of Texas at San Antonio Computer Science Program offers a sophomorelevel course called Computer Organization II which is required of all undergraduate computer science majors. We use the text Structured Computer Organization by Tanenbaum [8]. The background of the students taking this course includes an introductory course in which they learn to program in C, a data structures course, also in C, and a circuit design course. The course covers CPU organization, the instruction cycle, memory, microprogramming, instruction formats and ....

A. S. Tanenbaum, Structured Computer Organization, Third Edition, Prentice Hall, 1990.

....additional instructional material are available via the web. 1 Introduction The University of Texas at San Antonio computer science degree program includes a required course at the sophomore level called Computer Organization II that uses the text Structured Computer Organization by Tanenbaum [1]. The students in this course have previously taken an introductory programming course in C, a data structures course, also in C, and a circuit design course. Computer Organization II covers CPU organization, the instruction cycle, memory, microprogramming, instruction formats and types, ....

....or instruction are incorporated into the graphical display. The prototype can be run through a browser [9] but the Mac 1 memory cannot be changed. Appendix: Details of the Mic 1 and Mac 1 Machines This appendix provides an overview of the Mic 1 and Mac 1 from Section 4. 2 in Tanenbaum s book [1]. Refer to Figure 1 of the paper during the discussion. The Mic 1 instruction cycle consists for four subcycles. On the first subcycle the microprogram counter (MPC) addresses one of the 256 possible words in the control store, and this value is stored in the microinstruction register (MIR) On ....

A. S. Tanenbaum, Structured Computer Organization, Third Edition, Prentice Hall, 1990.

....for the students used as efficiently as possible. It seems to be an impossible task to have sufficiently many computers available to the students. 3. THE STUDY The mechanisms were tried in an ordinary first year Computer Architecture course at X University during spring 1994. We used Tanenbaum [7] for general theory and Ford Topp [8] for assembly language programming on Mc680x0. We had 65 students (6 women) enrolled this year, out of which 52 (5 women) passed. No changes were made to the content of the course, the duration (10 weeks) or to the number and content of compulsory labs and ....

Tanenbaum, A. S., Structured Computer Organization, Prentice--Hall, third edition, 1990.

....CPUs, and two curves fit to the data. The points represent the Intel 4004 (12 bits) Intel 8008 (14 bits) Intel 8080 (16 bits) Intel 8086 (20 bits) Motorola 68000 (32 bits) Intel 80386 (48 bits) and MIPS R 4000 and HP 9000 700 (64 bits) The data come from [Siewiorek et al. 1982, page 5] [Tanenbaum 1990], and [Glass 1991] noticed that available virtual address space has grown by about one bit per year [Siewiorek et al. 1982] but their conclusions are based on old data. In Figure 3, we plot the virtual address bit count of microprocessor chips against the first year of introduction, for those ....

A. Tanenbaum. Structured Computer Organization, page 27. Prentice Hall, third edition, 1990.

....concurrent memory access in shared memory architectures [2, 10] the cited sources use combining networks to solve this problem. In the world of uniprocessors, one encounters essentially the identical problem in several scenarios, including the regulation of direct memory access (DMA) devices [12]; in this case, the smaller number of competitors allows one to use bus controllers to arbitrate conflicts. A less obvious instance of asynchronous competition arises in the design of (sequential) circuits, where one must employ sophisticated techniques to avoid race conditions, i.e. situations ....

.... simplicity of message routing in circuit switched networks, as compared to the complexity of, say, wormhole routing [6] In the world of uniprocessors, one encounters essentially the same tension in the dichotomy between parallel I O protocols, on the one hand, and serial ones, on the other [12]. 3.3. Pipelining via loop unfolding. Elementary computation theory establishes that one can unwind loops in abstract machines in order to pipeline computations. It takes a sophisticated leap, though, to translate this easy theoretical result into an algorithm that automatically transforms any ....

A.S. Tanenbaum (1990): Structured Computer Organization (3rd ed.) Prentice Hall, Englewood Cliffs, N. J.

....resuming the program. Keywords: interrupt mechanism, nested precise processing, pipelined design, proof of correctness 1 Introduction Up to date computer systems provide fast I O, virtual memory and support the full IEEE floating point standard. All that calls for a powerful interrupt mechanism [6, 7]. After invoking the operating system, it must be possible to resume the program at the instruction which caused the problem (preciseness) Furthermore, interrupt handlers must be able to call or interrupt each other (nesting) because a slow device could otherwise block a faster device longer ....

....to be obeyed, but the design of protocols of any kind is one of the most error prone activities in computer science. Thus, it is no wonder that interrupt handling is acknowledged to be a particularly hard part of machine design ( 1] p. 214) and that most publications on interrupt handling [1, 5, 6, 7, 8, 9, 10] sketch only parts of those mechanisms. Usually, they ignore the interactions of the software protocol and the hardware support, or restrict the solutions to the sequential processing of interrupts. However, those simplifications can by no mean be tolerated in modern operating systems [6, 7] The ....

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A.S. Tanenbaum. Structured Computer Organization. Prentice-Hall International, Inc., 1990.

....(i.e. design) errors. A central theme of computer organization is that hardware and software are logically equivalent, and that the design decision to put certain functions in hardware and others in software is made on the basis of such factors as cost, speed, and frequency of expected changes [4]. Reconfigurable devices such as Field Programmable Gate Arrays (FPGAs) have altered this distinction between hardware and software. These devices, which represent a revolution in custom digital logic design, consist of programmable logic cells and interconnections. Previously, only the most ....

Tanenbaum, A., Structured Computer Organization, Prentice-Hall, Englewood Cliffs, New Jersey, 1976.

....it is not true that all processes rely upon the results obtained from a preceeding process. This allows some processes to be run in parallel with each other. Processes from the same program that are running at the same time are said to be running in parallel [Deitel, 1990; Kumar et al. 1994; Tanenbaum, 1990]. There are two types of parallel execution, logical and physical. Logical parallelism is when a parallel program is running on a uniprocessor time sharing system. The parallel processes have their own time slice, process states and other data associated with a process. It is impossible to ....

....own time slice, process states and other data associated with a process. It is impossible to determine which parallel processes is using the CPU at any given time. The program behaves as if it has parallel processes but is running in a pseudo parallel manner [Bal, 1990; Gough and Mohay, 1988; Tanenbaum, 1990]. Physical parallelism is when each process executes at the same time as each other but each process has access to a separate CPU. This is the concurrent execution of processes [Ben Ari, 1990; Goscinski, 1991; Gough and Mohay, 1988; Tanenbaum, 1990] It is well documented that parallel execution ....

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Tanenbaum, A.S. (1990) Structured Computer Organization, London: Prentice- Hall International (UK) Limited.

....or less simultaneously. 1.2.5 From Algorithms to Languages to Hardware There are at least three fundamental sources of parallelism: the algorithm, the programming language, and the hardware. For each of these there is an associated virtual machine with its own language and computational model [62]. For the virtual machine at the algorithm level, there is an abstract parallel computational model. This model usually conforms to either the SIMD or MIMD organization, but can contain elements of both. Communication strategies, synchronous vs. asynchronous processors, and shared vs. non shared ....

Tanenbaum, A. S. Structured Computer Organization. Prentice-Hall, 1984.

....leads at least at this point to a topological difference between routing of messages in the specification and in the implementation. Maybe the interaction model is not expressive enough. The deadlock found is not special, it can be characterised as as a deadlock due to race conditions, see e.g. [T84]. We expect race conditions to occur often in a system of multiple cooperating components and with a user that interfaces to more than one of these components, and suggest to pay extra attention to the avoidance of race conditions in the design of these systems. In this report the ESC P is ....

A.S. Tanenbaum. Structured Computer Organization. Prentice--Hall, 1984.

....top of each other. 67 B.2 A typical disk structure (yet the track width is much enlarged) 68 6 LIST OF FIGURES September 1994 Computer Systemen en Applicaties List of Tables 1. 1 A possible anatomy of the modern digital computer (after (Tanenbaum, 1984)) 9 2.1 BSD and SysV implementations of Unix operating systems. 14 3.1 Names of the highest level Internet domains. 34 3.2 The ISO OSI reference model for networking. 34 4.1 The history of ....

....letters for his boss on a Mac computer. In this chapter, and throughout this book, we ll adopt a not so shocking view on computer systems: the hierarchical, layered structure. This layered structure describes increasing levels of complexity of viewing a computer system. In this we follow Tanenbaum (Tanenbaum, 1984) and many authors since then. Off we go. 1.2 Structure 1: Layers of computation To get a better understanding of the computer s inner workings, the layered structure as shown in table 1.1 is useful to breaks a computer system down into smaller parts. Although the Level Abstraction 6 high level ....

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Tanenbaum, A. S. (1984). Structured Computer Organization. Prentice-Hall Inc., Englewood Cliffs, N. J. 07632.

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Andrew S. Tanenbaum. Structured Computer Organization, chapter 2. PrenticeHall, Inc., fourth edition, 1999.

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A. Tanenbaum. Structured computer organization, Prentice-Hall, 1984.

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Tanenbaum,A. Structured Computer Organization. Fourth Edition, Prentice Hall, New Jersey, 1999.

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A. Tanenbaum. Structured Computer Organization, page 27. Prentice Hall, third edition, 1990.

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A. S. Tanenbaum, Structured Computer Organization, 2nd edn, Prentice-Hall, 1984.

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A.S. Tanenbaum, Structured computer organization, 2 nd ed Prentice-Hall 1984

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A. Tanenbaum, Structured Computer Organization, PrenticeHall, Englewood Cliffs NJ, 1990.

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A. Tanenbaum, Structured Computer Organization, PrenticeHall, Englewood Cliffs NJ, 1990.

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Tanenbaum, Andrew S., Structured Computer Organization, Prentice-Hall, 1990.

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Tanenbaum, A. S. (1990). Structured Computer Organization. Prentice-Hall International, third edition.

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A.S. Tanenbaum (1984). Structured Computer Organization. Prentice-Hall, Inc., Englewood Cliffs, NJ.

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Andrew S. Tanenbaum. Structured Computer Organization. Prentice Hall, third edition, 1990.

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Andrew S. Tanenbaum, 1990, "Structured Computer Organization"

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Andrew S. Tanenbaum. Structured Computer Organization. Prentice-Hall, third edition, 1990.

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