Susan A. Mason: "SBus Handbook", Sun Microsystems, Inc. (1994) Home/Search Document Not in Database Summary Related Articles Check |
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Gigabit Network with Cooperative Functions for General Purpose.. - Kunisawa (1997) (Correct)
....controller directly access host workstation s I O bus, the actual overhead is closely related to the overhead of protocols used by the I O bus. Similarly, remote memory access may require page tables stored in main memory. On this project, the interface controller is designed to hook into SBus[1] and used with Sun SparcStation 20 (SS20) SS20 drives SBus at 25MHz clock. As stated in previous section, this 4 A 20b control code is represented with K prefix (e.g. K28.5) whereas data code is represented with D prefix (e.g. D28.5) FC 1 defines K28.5 D21.4 D21.5 D21.5 sequence as IDLE, ....
Susan A. Mason: "SBus Handbook", Sun Microsystems, Inc. (1994)
An FPGA Based Reconfigurable Coprocessor Board.. - Eatherton, Kelly, .. (1995) (1 citation) (Correct)
....the system implementations are done manually in VHDL. However, our goal is to use the Psi Compiler to generate synthesizable VHDL code for high performance array address generation and microcode for the DSP chip. The Chameleon Coprocessor is designed to follow the IEEE 1496 1993 SBUS specification[5]. The width of the card for slave mode transfers is 8, 16, or 32 bits. In master mode the card currently uses 32 bit wide transfers with burst sizes of 1, 2, 4, 8, or 16 words. Direct virtual memory access (DVMA) is used for the transfers allowing the card to work independently of the Sun ....
Mason, S., Sbus Handbook, SunSoft Press, 1994
RACE: A Reconfigurable and Adaptive Computing Environment - Smith (1997) (Correct)
....which is used for co processing applications. The following sections describe in detail each component of the RACE system. 3.1 Workstation The workstation that is used to interface with RACE is a Sun Sparc IPC workstation running SunOS 4.1.3. The workstation s internal bus uses the SBus protocol[47], which is an industry open standard. The SBus can transfer data up to 16, 32 bit word bursts or double word bursts of 64 bits (extended mode) In a Sparcstation, the SBus frequency is 25MHz. Ideally, the SBus can transfer a word per clock, which equals to 100MB per second (168MB in extended ....
....word bursts or double word bursts of 64 bits (extended mode) In a Sparcstation, the SBus frequency is 25MHz. Ideally, the SBus can transfer a word per clock, which equals to 100MB per second (168MB in extended mode) In practice on an IPC, typical bus transfer rates are about 25MB per second [47] since it can only handle up to 4 word bursts. 3.2 DPS 1 Interface The interface between the RACE co processing architecture and the workstation is a DAWNVME Products DPS 1 DMA SBus prototyping board. The DAWN board has an LSI Logic L64853A Enhanced SBus DMA Controller [43] as well as an 28 LSI ....
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Susan A. Mason. SBus Handbook. SunSoft Press, 1994.
Mechanisms for Distributed Shared Memory - Reinhardt (1996) (4 citations) (Correct)
....exit from the hardware business. After this avenue closed, we selected the Myricom Myrinet as the fastest commercially available interconnect at the time. Each node connects to the Myrinet network using a standard Myrinet host interface card. This card plugs into the SBus, Sun s standard I O Bus [Mas94] Most of the interface s functionality including a simple processor and a DMA engine is contained on a single chip, the LANai. The card also has 128 KB of SRAM to store the LANai processor s code and data. The host processors can access the LANai s SRAM directly using uncached memory ....
Susan A. Mason. SBus Handbook. SunSoft Press, 1994.
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