J. Savir, G. S. Ditlow, and P. H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C-33, pp. 1041-1045, Jan.1984.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the steady state probabilities is seriously impaired. Table 2: First order vs. second order model using KMS alg. Second order First order Total PIs #(x,s) #s Total #(x,s) #s MAX MEAN power Circuit FFs power bbara 4 4 28 3 747.38 86 10 49.40 35.91 786.53 bbtas 2 3 18 6 337.75 20 6 55.70 24.28 345.78 dk17 2 3 6 2 1439.71 18 7 37.48 29.96 1313.78 donfile 2 5 9 5 3020.55 14 6 52.70 26.76 2943.15 exl 9 5 769 11 3165.66 1596 11 50.00 18.03 3082.86 planet 7 6 192 34 8550.92 3527 48 513.79 67.14 5429.B sand 11 5 977 32 7883.13 17169 32 103.57 24.49 3162.71 s1196 14 18 1536 329 7027.45 1918 ....

....probabilities is seriously impaired. Table 2: First order vs. second order model using KMS alg. Second order First order Total PIs #(x,s) #s Total #(x,s) #s MAX MEAN power Circuit FFs power bbara 4 4 28 3 747.38 86 10 49.40 35.91 786.53 bbtas 2 3 18 6 337.75 20 6 55.70 24.28 345.78 dk17 2 3 6 2 1439.71 18 7 37.48 29.96 1313.78 donfile 2 5 9 5 3020.55 14 6 52.70 26.76 2943.15 exl 9 5 769 11 3165.66 1596 11 50.00 18.03 3082.86 planet 7 6 192 34 8550.92 3527 48 513.79 67.14 5429.B sand 11 5 977 32 7883.13 17169 32 103.57 24.49 3162.71 s1196 14 18 1536 329 7027.45 1918 342 133.71 4.17 ....

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J. Savir, G.S. Ditlow, and P.H. Bardell, 'Random Pattern Testability', in 1EEE Trans. on Computers, vol. C-33, Jan. 1984.

.... tree circuits which consist of simple gates, the exact signal probabilities can be computed during a single post order traversal of the network [5] An algorithm, known as the cutting algorithm, which computes lower and upper bounds on the signal probability of reconvergent nodes is presented in [6]. The algorithm runs in polynomial time in the size of the circuit. Ercolani et al. present in [7] a procedure for propagating the signal probabilities from the circuit inputs toward the circuit outputs using only pairwise correlations between circuit lines and ignoring higher order correlations. ....

J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Trans. Comput., vol. C-33, pp. 1041--1045, Jan. 1984.

.... in are at distance two from each other and any vertex is at the same distance from all the vertices in Hence the vertices in are not distinguishable if Finally, we address the problem of code construction for hexagonal and triangular meshes, the former topology having received attention recently [23]. Every hexagonal (triangular) mesh has three (six) neighbors. Fig. 3 shows these topologies with the codewords (shaded) for vertex identification with For the hexagonal mesh, the number of codewords , where is the total number of vertices in the graph. Every codeword is covered only by itself ....

J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Trans. Comput., vol. C-33, pp. 79--80, Jan. 1984.

....(BIST) is an important testing technique which enables at speed and on site testing while requiring neither automatic test generation nor expensive test equipment. In general, pseudo random test patterns are generated by an LFSR and circuit responses are compressed by a signature analysis register [1]. Maximum fault coverage can be achieved at significant area and performance overhead cost by configuring all flip flops as test registers. At the other extreme, very low overhead can be achieved with a fault coverage penalty by inserting test registers only at primary inputs and outputs. Partial ....

J. Savir, G. S. Ditlow, and P. H. Bardell, "Random Pattern Testability, " IEEE Transactions on Computers, Vol. C-33, No. 1, January 1984, pp. 79-90.

....almost everywhere in the area of deterministic and random testing of combinational circuits. This knowledge is even more valuable for sequential circuits. For combinational circuits, highly efficient tools have been developed for that task. Some base on sophisticated approximation strategies [8, 11, 17], other compute the exact value [7, 10, 12] An other important application of signal probabilities is switching activity analysis as shown e.g. in [16] Even in the case of a combinational circuit, the exact algorithms have exponential time complexity measured in the number of inputs. So, we do ....

J. Savir, G.S. Ditlow, and P.H. Bardell. Random pattern testability. IEEE Trans. on Comp., 33:79--95, 1984.

....cost and the results of our experiment on the benchmark circuits show that it is very effective in providing fault coverage close to the maximum obtainable fault coverage using random patterns with full scan. 1 Introduction In testing combinational circuits, both deterministic and random testing [14, 1] methods have been used. Deterministic testing has the advantage of generating fewer test vectors (i.e. shorter test application This work was supported in part by the National Science Foundation grant MIP 9307830 and a grant from the AT T Foundation. y The author Lama Nachman at present is with ....

....each of the circuit to a partially scanned circuit by scanning some of the flip flops in the circuit. The total number of flip flops as well as the number of selected flip flops in the scan chain are shown in Table 5 (columns 2 and 3) The selection of the scan flipflops was obtained from [14]. Note that the selection of flip flops for inclusion in the scan path is not a sub Table 4: Comparison of the hold method with deterministic test generation systems Hold Deterministic Test Method Generation circuit (Table 3) Systems FC ( FC ( ATPG s382 86 90.7 DUST s444 80.4 87.8 Lee ....

J. Savir, G. Ditlow, and P. Bardell, "Random Pattern Testability," IEEE Trans. on Computers, vol. C-33, no. 1, pp. 79--90, January 1984.

....switch, circuit, fault) it is complete only when the circuit behavior for all possible inputs is studied. In such a case the input vectors that represent various input combinations are dynamic attributes that capture circuit usage as they propagate through the various nodes. Testability analysis [BPH84, SDB84, JA84, LBdGG87] which is sometimes viewed as an alternative to fault simulation, is another problem that relies on a dynamic attribute. The objective here is to project the cost of testing by predicting the number of random test patterns needed to achieve high fault coverage. High fault coverage is usually ....

....an error in the probability computation will affect H w and consequently the spatial entropy. Exact 1 probability computation in circuits with reconvergent fanout has been extensively studied in the areas of fault simulation [BPH84, MJ90, AS87] test generation [HM86] and testability analysis [SDB84, SPA85, JA84]. b a c f = ab ac ab [abc ,abc] ab c,abc] a b c ac bc AND AND OR f =ab ac [abc,ab c,abc ] 2 8 2 8 (3 8) 7 16 ac Figure 3.8: Reconvergent Fanout An Example We begin by reviewing the idea of reconvergence. This is illustrated with a simple example in Figure 3.8. The gate level implementation ....

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J. Savir, G. S. Ditlow, and P. H. Bardell. Random Pattern Testability. IEEE Transactions on Computers, C-33:79--90, January 1984.

.... circuits are dominated by the reconvergent fan out (RFO) problem; over the years, people working in testing, timing and more recently in power areas have been faced with difficult problems arising from the fan out reconvergence, mostly when they want to calculate the signal probability [3] [4], 5] In general, accounting for structural dependencies is a difficult task but when combined with temporal dependencies on circuit inputs is even harder; unfortunately, power estimation techniques must consider all of these dependecies in order to produce accurate results. Let us consider a ....

J. Savir, G. S. Ditlow, and P. H. Bardell, 'Random Pattern Testability', in IEEE Trans.on Computers, vol. C-33, Jan.1984

....III A. Probability Propagation For static signal probabilities (as opposed to probability waveforms) propagation has been addressed by several researchers. The solution in [8] uses symbolic analysis, that in [9] gives an algorithm with several suggested heuristics to improve efficiency, while [11] suggests an efficient fresh approach that gives bounds on the probabilities rather than exact probabilities. The problem is of linear complexity for circuits with no reconvergent fanout or feedback, but becomes exponential otherwise. In fact, it s easy to prove that if reconvergent fanout and ....

J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Transactions on Computers, vol. C-33, no. 1, pp. 79--90, January 1984.

....calculations are significant for most of the analyzed benchmarks. I. INTRODUCTION In the last decade, probabilistic approaches have received a lot of attention as a viable alternative to deterministic techniques for analyzing complex digital systems. Logic synthesis [1] verification [2] testing [3] and more recently, low power design [4] have benefited from using probabilistic techniques. In particular, the behavior of FSMs has been investigated using concepts from the Markov chain theory. Studying the behavior of the Markov chain provides us with different variables of interest of the ....

J. Savir, G.S. Ditlow, and P.H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C-33, Jan. 1984.

....values can be more than 100 off from the correct ones. 3 1. Introduction In the last decade, probabilistic approaches have received a lot of attention as a viable alternative to deterministic techniques for analyzing complex digital systems. Logic synthesis [1] verification [2] testing [3] and more recently, low power design [4] have benefited from using probabilistic techniques. In particular, the behavior of FSMs has been investigated using concepts from the Markov chain (MC) theory. Studying the behavior of the MC provides us with different variables of interest of the original ....

J. Savir, G.S. Ditlow, and P.H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C33, Jan. 1984.

.... of the network [2] Alternatively, one may use a graph based algorithm to compute the exact values of signal probabilities using Shannon s expansion [3] The cutting algorithm, which computes lower and upper bounds on the signal probability of reconvergent nodes was developed and presented in [4]. Also, the Ordered Binary Decision Diagram representation (OBDD) was used for computing the signal probability in [6] and [7] The spatial correlations among different signals are modelled in [5] where a procedure is described for propagating signal probabilities from the circuit inputs toward ....

J. Savir, G. S. Ditlow, and P. H. Bardell, `Random Pattern Testability', in IEEE Trans.on Computers, vol. C-33, Jan.1984

....[4] provides an extension to [2] called the weighted averaging algorithm; this approach attempts to take into account the first order effects of reconvergent fanout stems in the variable support of the node. It is linear in the product of the number of circuit inputs and the size of the circuit. [5] gives an algorithm, known as the cutting algorithm, which computes lower and upper bounds on the signal probability of reconvergent nodes by cutting the multiple fanout reconvergent input lines and assigning an appropriate probability range to the cut lines and then propagating the bounds to all ....

J. Savir, G. S. Ditlow, and P. H. Bardell, 'Random Pattern Testability', in IEEE Trans.on Computers, vol. C-33, Jan.1984

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J. Savir, G. S. Ditlow, and P. H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C-33, pp. 1041-1045, Jan.1984.

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J. Savir, G. Ditlow, and P. Bardell. Random pattern testability. IEEE Transactions on Computers, 33(1):1041--1045, jan 1984.

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J. Savir, G.S. Ditlow, and P.H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C-33, Jan. 1984.

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J. Savir, G. S. Ditlow, and P. H. Bardell, 'Random Pattern Testability', in IEEE Trans.on Computers, vol. C-33, Jan.1984

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J. Savir, G. S. Ditlow, and P. H. Bardell, 'Random Pattern Testability', in IEEE Trans.on Computers, vol. C-33, Jan.1984

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J. Savir, G. S. Ditlow, and P. H. Bardell, `Random Pattern Testability', in IEEE Trans. on Computers, vol. C33, pp. 1041-1045, Jan. 1984.

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J. Savir, G. Ditlow, and P. Bardell. " Random pattern testability. " IEEE Transactions on Computers, 33(1):1041--1045, January 1984.

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J. Savir, G. S. Ditlow, and P. H. Bardell, "Random Pattern Testability," IEEE Transactions on Computers, Vol. C-33, No. 1, January 1984, pp. 79-90.

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J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," Transactions on Computers, vol. C-33, no. 1, pp. 79--90, 1984.

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J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Transactions on Computers, pp. 79--90, January 1984.

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J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Transactions on Computers, pp. 79--90, January 1984.

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J. Savir, G. S. Ditlow, and P. H. Bardell, "Random pattern testability," IEEE Trans. Computers, pp. 79--90, January 1984.

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