Tetsuo Kawano, Shigeru Kusakabe, Rin ichiro Taniguchi, and Makoto Amamiya. Fine-grain multi-thread processor architecture for massively parallel processing. In Proc. of the First Intl. Symp. on High-Performance Computer Architecture, pages 308--317, Raleigh, N. Caro., Jan. 1995. 180  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Also dynamic and irregular applications might cause excessive waste of cycles when mapped to a blocking thread model. 142 8. 2 Software Multithreaded Systems In the classical strict data flow model of computation, an instruction is enabled for execution when all its operands are available [66, 85, 63, 65, 68, 47, 155, 70, 77, 127, 130, 86, 123, 125, 12, 97, 133, 132, 124, 15, 17, 45, 57, 150, 140]. To enforce the enabling condition, the instructions that produce such operands must be able to send a synchronization signal to all the instructions that will consume the recently produced result. This model proved unyielding for the implementation of machines based on current standard ....

Tetsuo Kawano, Shigeru Kusakabe, Rin ichiro Taniguchi, and Makoto Amamiya. Fine-grain multi-thread processor architecture for massively parallel processing. In Proc. of the First Intl. Symp. on High-Performance Computer Architecture, pages 308--317, Raleigh, N. Caro., Jan. 1995. 180

....a packet in CU, one memory read (RD ) for continuation data and one memory write of packet data (WD ) occur. Where, RD is the number of cycles used in read access from RB, and WD in write access into RB. In KUMP D, CPU uses memory bus 3 Performance evaluation of the Datarol II is discussed in [11] to issue an FMP instruction (I K ) FMP writes the contents of a message to the memory on receiving a message (WK ) Where, I K is the number of memory bus cycles used when CPU issues an FMP instruction, RK in read access from memory, and WK in write access into memory. Table 4. # of bus ....

T. Kawano, S. Kusakabe, R. Taniguchi, and M. Amamiya, "Fine-grain multi-thread processor architecture for massively parallel processing," Proc. IEEE HPCA'95 pp. 308--317 (1995).

....at various levels including fine grain parallelism. However, since it is difficult to implement such a language on stock parallel machines, efficient implementation could be achieved only using special fine grain parallel machines. Therefore, a special finegrain parallel machine, Datarol[10], is one of our implementation targets. However, in order to make V a generally practical language, commercially available stock parallel machines are also used for implementation. In our implementation approach, the compiler generates fine grained virtual machine codes, and then schedules the ....

T. Kawano, S. Kusakabe, R. Taniguchi and M. Amamiya "Fine-grain Multi-thread Processor Architecture for Massively Parallel Processing" Proc. of IEEE High Performance Computer Architecture, pp. 308--317, 1995.

....had a drawback in the sense that it did not use the high speed registers and the pipeline technique used in conventional RISC processors. In order to eliminate this drawback, we have developed the Datarol II processor architecture, which was an optimized version of original Datarol architecture[3, 10, 11]. The Datarol II executes finegrain threads by means of a program counter based execution pipeline by using high speed registers. We are now building a prototype multithread machine KUMP D (Kyushu University Multi media Processor on Datarol II) which is oriented towards high speed multi media ....

....and by reference data access concepts, which made the machine free from copying data and redundant token matching. Although having reduced the redundancies of control, the Datarol had a weak point for the sequential program execution, and, in order to overcome this weak point, Datarol II[3, 10, 11] was designed to execute multiple sequential threads efficiently. However, all these architectures required a special hardware design, and could not get the benefit of the commercially available microprocessor technology. Other dataflow projects like in MIT[12, 13] ETL[14, 15] EARTH[8] and ....

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T.Kawano, R.Taniguchi and M.Amamiya, " Finegrain Multi-thread Processor Architecture for Massively Parallel Processing," Proc. First IEEE Symposium High-Performance Computer Architecture (HPCA'95), pp.308-317, 1995.

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