V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Design Automation Conf., pages 197--204, 1988. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Formal Verification of a Basic Circuits Library - Berg, Jacobi, Kroening (2001) (Correct)
.... zero counter n = 2 m n log n barrel shifter n = 2 m n log n log n logic left shifter n n log n log n logic right shifter n n log n log n Table 1: The components contained in the library in increasing complexity verification of an adder using various verification systems is described in [9]. In [10] Bryant verifies fixed size arithmetic circuits against a mathematical specification. Given a reference design and assuming its correctness, it is state of the art to automatically verify equivalence with a new design. There are several approaches to this, e.g. boolean equivalence ....
V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Proceedings of the 25th ACM/IEEE conference on Design Automation, pages 197--204, 1988.
A Method for Approximate Equivalence Checking - Thornton, Drechsler, Gunther (2000) (Correct)
....incorporation of the Haar spectral coefficients in our approach allows for further information about the two candidate functions to be exploited. This problem has applications in logic synthesis and is also of concern in verification systems where two representations of a function are compared [2, 3, 10, 13]. Two abstractions of a circuit resulting from different optimization phases of a logic synthesis system (e.g. f(X) and g(Y ) may need to be checked to determine if f(X) g(Y ) This is applicable for methods that express state machines as BDDs or MDDs as well as for the verification of purely ....
V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Design Automation Conf., pages 197--204, 1988.
Probabilistic Equivalence Checking Using Partial Haar.. - Thornton, Drechsler.. (Correct)
....speed, etc. Determining the appropriate set of library cells , fg i g, can be accomplished via the application of an equivalence checking technique. The equivalence checking function is also of concern in verification systems where two representations of a function are compared [3] 5] 14] 15] [17]. Two abstractions of a circuit This work was supported in part by NSF grants CCR 9633085, SBE 9815371 and DAAD grant 315 PPP gu ab resulting from different optimization phases of a logic synthesis system (e.g. f(X) and g(Y ) may need to be checked to determine if f(X) g(Y ) This is applicable ....
V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Design Automation Conf., pages 197--204, 1988.
Structuring and Automating Hardware Proofs in a.. - Kumar, Schneider, Kropf (1993) (10 citations) (Correct)
.... Keywords: hardware verification, higher order logic 1 Introduction The past decade has witnessed the spiralling of interest within the academic community in developing methods for formal hardware verification, i.e. to formally prove that a given implementation satisfies its specification [1, 2, 3]. It is desirable, that the implementation description and the specifications are at different abstraction levels or within different domains (behavioural, structural, or physical) in order to enforce an incremental design philosophy used in designing complex circuits [4, 5] The problems that ....
V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In 25th Design Automation Conference, pages 197--204, 1988.
Experiments in Automating Hardware Verification using.. - Cantu, Bundy, Smaill.. (1996) (2 citations) (Correct)
....provers like HOL and Nuprl are also fully expansive systems. 5.1 Nqthm Most of the circuits in the table have been verified elsewhere using Nqthm. For instance, the n bit adder was verified (big endian) in half a man day, where the discovery of the required lemmas was the most difficult part[17]. A combinational processing unit (alu and shifter) was verified by Warren Hunt as part of the verification of the FM8501 microprocessor. This processing unit is verified in 3 theorems corresponding to the word, natural number, and two s complement interpretations. It took about 2 months effort, ....
V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Proceedings of the 25th ACM/IEEE Design Automation Conference, pages 89-96. IEEE, 1988. This article was processed using the L a T E X macro package with LLNCS style
Probabilistic Equivalence Checking Using Partial Haar.. - Thornton, Drechsler.. (Correct)
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V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Design Automation Conf., pages 197--204, 1988.
A Method for Approximate Equivalence Checking - Mitch Thornton Rolf (2000) (Correct)
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V. Stavridou, H. Barringer, and D.A. Edwards. Formal specification and verification of hardware: A comparative case study. In Design Automation Conf., pages 197--204, 1988.
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