H. Mehta, R. Owens, M. Irwin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proc. ISLPED---Int. Symp. Low Power Electronics and Design, 1997, pp. 72--75.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....UCB1200 Analog Digital Sensors Microphone and Speakers Memory: Flash SRAM Display DC DC Converter RF StrongARM SA 1100 Figure 1. SmartBadge Architecture addition, several other optimizations have been suggested, such as energy efficient register labeling during the compile phase [13], procedure inlining and loop unrolling [14] as well as instruction scheduling [15] Work presented in [16] applies a set of compiler optimizations concurrently and evaluates the resulting energy consumption via simulation. All of these techniques focus on automated instructionlevel optimizations ....

H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, D. Ghosh, "Techniques for Low Energy Software", International Symposium on Low Power Electronics and Design, pp. 72---75, 1997.

.... running software: the locality of reference exhibited, the frequency of bus memory requests, the chip units on active use such as floating point unit(FPU) or digital signal processor(DSP) even the data structure choices affect the switching frequency in integrated circuits, hence the parameter ff [14]. Finally, it is highly likely and desirable that aggressive low power techniques at the circuit, microarchitecture, compiler and OS scheduler levels are to be integrated in a common framework, which points to the necessity of considering (potentially) different power dissipation functions for ....

H. Mehta, R. M. Owens, M. J. Irwin, R. Chen and D. Ghosh. Techniques for low Energy Software. In Proceedings of the 1997.

....assembly level such as instruction reordering, reduction of memory operands, operand swapping in the Booth multiplier, efficient usage of memory banks, and series of processor specific optimizations. Several other optimizations such as energy efficient register labeling during the compile phase [13], procedure inlining and loop unrolling [14] as well as instruction scheduling [15] have also been suggested. In other work [16] various compiler optimizations are applied concurrently and the resulting energy consumption is evaluated via simulation. All of these techniques focus on automated ....

H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, D. Ghosh, "Techniques for Low Energy Software", International Symposium on Low Power Electronics and Design, pp. 72-75, 1997.

....the tasks can meet their deadlines and also recover from potential failures. If a failure occurs, we set the processor to operate at maximum speed (and consequently maximum energy consumption) to re execute the lost computation. Power management has recently attracted a large body of research [7, 11, 12, 23, 24, 27, 28, 32, 35 37]. This increasing attention has been motivated initially by the limitations on battery life in portable devices. There are several aspects to the problem, including controlling the power of the processor, display, disk subsystem, and memory [6] The interactions of these techniques with failure ....

H. Mehta, R. Owens, M. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proceedings of the 1997.

....study how to generate low power software for DSP processors. 2 Related Research In the area of low power, researchers have developed architecture level models to be used in a simulation environment or higher level tools. Memory components, controllers [5] instruction registers of microprocessors [7,3], are examples of some components that are known to dissipate signi. cant power in addition to datapath components. Researchers have tried to schedule operations [5] or swap operands [1] to reduce data bit switching. Researchers have also employed parallel instructions to improve performance ....

H.Mehta, R.Owens, M.Irwin, D.Ghosh, "Techniques for low energy software", ISLPED , p72-75, 1997.

....of instruction level power models. Concerning low power scheduling algorithms, some approaches have been proposed by Tiwari et al. 5 7] but these works target either scalar or DSP processors with packed operations and their extension to VLIW code generation is not straightforward. Other authors [11,12] introduced power optimization methodologies from a software level perspective, such as pre processing and restructuring the source code to reduce the power consumption of the executable code. Other techniques, such as spatial and temporal scheduling, have been proposed by Lee et al. 13] Spatial ....

H. Mehta, R. Owens, M. Irwin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proceedings of the International Symposium on Low Power Electronics and Design, August 1997, pp. 72--75.

....Thus, loop unrolling and procedure inlining were used to reduce the number of processor cycles, while data localitywas improved by cache size optimization. Several papers have addressed the problem of assessing the impact of source code transformations on families of hardware architectures [5, 6, 7]. In these works, instruction level simulation is employed to measure the e ects of code transformation on energy. Without exception, these works have concluded that the optimal transformation depends on the characteristics of the processor and of the memory system. On the other hand, pure ....

H. Mehta,R.Owens, M. Irwin, R. Chen, and D. Ghosh, \Techniques for Low Energy Software", ISLPED, pp.72-75, 1997

....technique schedules instructions in each basic block in a way that binary representations of consecutive two machine instructions are less different while maintaining the control data dependencies of the original program. The third approach is the instruction encoding. Register relabeling [8] assigns register numbers of instructions so that more frequently consecutive register numbers have a smaller Hamming distance, thus reducing the switching activity of the instruction bus and decode logic. The instruction scheduling and instruction encoding techniques also reduce the switching ....

H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proc. of Int. Symp. on Low Power Electronics and Design, pages 72--75, 1997.

....techniques that enable energy reduction for software, since an increasing number of applications are powered by batteries. Therefore, recent studies have been focusing on developing techniques to reduce the energy consumption at various levels, including program optimization for low power [10, 15, 20]. Such low power program optimization techniques require a detailed cost model represented in terms of energy consumption to direct the decisions on program transformations. We propose a technique to build an accurate energy consumption model at the instruction level, which can be used in ....

H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 72-75, August 1997.

....such as instruction reordering, reduction of memory operands, operand swapping in Booth multipliers, efficient usage of memory banks, and series of processor specific optimizations. Several other optimizations have been suggested, such as energy efficient register labeling during the compile phase [19], procedure inlining and loop unrolling [7] as well as instruction scheduling [27] Work presented in [20] applies a set of compiler optimizations concurrently and evaluates the resulting energy consumption via simulation. All of the techniques discussed above focus on automated instruction level ....

H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, D. Ghosh, "Techniques for Low Energy Software," International Symposium on Low Power Electronics and Design, pp. 72--75, 1997.

....(including processor and cache) In our studies, the processor and cache affect memory energy efficiency by influencing execution time and miss rate (the number of DRAM accesses) 2. 3 Related Work Architectural studies have examined the impact of software structure on power consumption [6, 34, 44]. Other architectural studies investigated processor design [4, 33, 39] focused specifically on the memory hierarchy [14, 17, 21, 36] or examined ways to optimize DRAM refresh counts [38] RDRAM was clearly designed to enable designers to create pools of devices in various power states, as it is ....

H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for Low Energy Software. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 72--75, August 1997.

....power management and experimental comparisons of management algorithms for a hard disk. 1. Introduction Low power consumption is an important goal in designing modern electronic systems. Most previous studies of low power techniques focused on either hardware (HW) 14] or software (SW) [12] to reduce power consumption. Dynamic power management (DPM) 2] is an effective approach to reduce power consumption without significantly degrading performance. DPM shuts down devices when they are not needed and wakes them up when necessary. Recently, Intel, Microsoft and Toshiba proposed the ....

H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for Low Energy Software. In International Symposium on Low Power Electronics and Design, pages 72--75, 1997.

....reordering, reduction of memory operands, operand swapping in the Booth multiplier, efficient usage of memory banks, and series of processor specific optimizations. In addition, several other optimizations have been suggested, such as energy efficient register labeling during the compile phase [14], procedure inlining and loop unrolling [10] as well as instruction scheduling [15] All of these techniques focus on automated instruction level optimizations driven by the compiler. Even though these techniques may be very helpful once integrated into an industrystrength optimizing compiler, ....

H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, D. Ghosh, "Techniques for Low Energy Software," Proceedings of ISLPED, pp. 72--75, 1997.

....such as instruction reordering, reduction of memory operands, operand swapping in the Booth multiplier, efficient usage of memory banks, and series of processor specific optimizations. Energy efficient register labeling during the compile phase has been suggested as an approach to optimization [5]. Procedure inlining and loop unrolling [12] as well as instruction scheduling [11] have also been investigated. Our cycle accurate energy consumption simulator presents an integrated framework that is fast enough and accurate enough to estimate the impact of software optimizations on any ....

H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, D. Ghosh, "Techniques for Low Energy Software," Proceedings of ISLPED, pp. 72--75, 1997.

....proposed is suspension of a speci c sub unit such as disk, memory, display, etc. based upon detection of prolonged inactivity. Several methods of extending battery lifetime within the operating system and middleware layer are discussed in (Tiwari et al. 1994, Chandrakasan and Brodersen, 1995, Mehta et al. 1997). Other techniques studied include power aware CPU scheduling (Weiser et al. 1994, Lorch and Smith, 1997) and page allocation (Lebeck et al. 2000) Within the application layer, the power conserving mechanisms tend to be application speci c such as database access (Imielinski et al. 1994, ....

....mechanisms that operate in conjunction with hardware policies. CPU scheduling techniques that attempt to minimize power consumption are presented in (Weiser et al. 1994, Lorch and Smith, 1997) The impact of software architecture on power consumption is studied in (Tiwari et al. 1994, Mehta et al. 1997). 8.2. Application Layer The application layer in a wireless system is responsible for such things as partitioning of tasks between the xed and mobile hosts, audio and video source encoding decoding, and context adaptation in a mobile environment. Energy eciency at the application layer is ....

Mehta, H., R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh: 1997, `Techniques for Low Energy Software'. In: Proc. of the International Symposium on Low Power Electronics and Design. pp. 72-75.

....the transition activity of the inputs to the functional units. After a sequence of rotations, we get the final schedule that both satisfies a predefined iteration bound and reduces power dissipation. Studies concerning low power design have proposed several different solutions. Irwin, et. al, [3] study the effect of several standard compiler techniques such as loop unrolling, software pipelining, and recursion elimination on power consumption. They show that software pipelining decreases the number of stalls by fetching instructions from different iterations. Hence, total energy ....

H. Mehta, Robert M. Owens, M. Irwin, R. Chen and D. Ghosh, "Techniques for Low Energy Software", International Symposium on Low Power Design, 1997, pp. 72-75.

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H. Mehta, R. Owens, M. Irwin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proc. ISLPED---Int. Symp. Low Power Electronics and Design, 1997, pp. 72--75.

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H. Mehta, R. M. Owens, M. J. Irvin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proc. Int. Symp. Low Power Electronics Design, 1997, pp. 72--75.

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H. Mehta, R. M. Owens, M. J. Irvin, R. Chen, and D. Ghosh, "Techniques for low energy software," in Proc. Int. Symp. Low-Power Electron. Design, 1997, pp. 72--75.

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H. Mehta, R. Owens, M. Irwin, R. Chen, and D. Ghosh, "Techniques for Low Energy Software", Proceedings of ISLPED, pp.72-75, 1997

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H. Mehta, R. Owens, M. Irwin, R. Chen, D. Ghosh, "Techniques for Low Energy Software," International Symposium on Low Power Electronics and Design , pp. 72-75, Aug 1997.

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H. Mehta,R.Owens, M. Irwin, R. Chen, and D. Ghosh, \Techniques for Low Energy Software", ########### ## ######, pp.72-75, 1997

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H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 72--75, August 1997.

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H. Mehta, R.M. Owens, M.J. Irvin, R. Chen, and D. Ghosh, "Techniques for Low Energy Software", International Symposium on Low Power Electronics and Design, pp. 72-75, 1997.

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H. Mehta, R. M. Owens, M. J. Irwin, R. Chen, and D. Ghosh. Techniques for low energy software. In Proceedings of the International Symposium on Low Power Electronics and Design, pages 72--75, August 1997.

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