R. Camposano. Path-Based Scheduling for Synthesis. IEEE TCAD, 10(1):85--93, January 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....step assignment, which will contribute towards the most homogeneous distribution is accepted at each step. This approach has been incorporated into high level synthesis systems as well [25] 9] Another type of scheduling method is referred to as path based scheduling in the literature [8]. This method has been proposed for scheduling control flow graphs. Paths of execution within the control data flow are handled individually. Each such possible path is scheduled independently in an optimal fashion. Then the final schedule is constructed by imposing the resource constraints and ....

R. Camposano. Path-based scheduling for synthesis. IEEE Trans. on Computer-Aided Design, 10:85--93, 1991.

....India Jan. 3 6, 1996. 17] J. berg, J. Isoaho, P. Ellervee, A. Jantsch, A. Hemani, A Rule Based Allocator for Improving Allocation Electronic System Design Laboratory vi of Filter Structures in HLS , In Proc. of the VLSI Design 96 Conference, pp 133 139, Bangalore, India, Jan. 3 6, 1996. [18] J. berg, P. Eles, A. Hemani, K. Kuchcinski, Z. Peng, Specifying Local Timing Constraints for HLS of Digital Systems in VHDL . In Proc of the 3rd Asian Pacific Conference on Hardware Description Languages (APCHDL 96) pp 145 149, Bangalore, India, Jan. 8 11, 1996. 19] P. Ellervee, A. Hemani, A. ....

....units. In telecommunication systems, targeted for routing, switching etc. the functionality is dominated by control decision and interactions with memory, with little or no arithmetic operations. There has been several suggestions on how to extend HLS to cope with control dominated functionality [17, 18, 19, 20, 21, 22]. While the work by W. Wolf [17] presents a model for performing behavioural synthesis, the other papers address the problem of global scheduling of the of the datapath operations into control states. Figure 1.4. The principles of High Level Synthesis X(15 downto 1) X(14 downto 0) Xin; ....

R. Camposano, "Path-based Scheduling for Synthesis", IEEE Transactions on Computer -Aided Design, Vol. 10, No. 1, pp. 85-93, January, 1991.

....functional specification that is mapped into a structural description through HLS techniques. Of special concern in the HLS step is the use of a sheduling algorithm well suited to the synthesis of control flow dominated behavioral compilers [5] In this case, the Dynamic Loop Scheduling (DLS) [6, 7, 8, 9] algorithm is employed. The resulting structural description is then used as input of the logical synthesis tool Synopsys [10] and finally the Opus [11] tool generates the circuit layout. In this work two protocols, the IPv6 and the AAL5 [12] are synthesized as a means to evaluate the complexity ....

Camposano, R., "Path-Based Scheduling for Synthesis", IEEE Transactions on CAD, vol. 10, pp. 85--93, Jan 1991.

....tasks, with a NEVER set containing all the software tasks, where the other tasks are all hardware tasks. So we design an algorithm to suit this specific problem. We take as input both the CDFG annotated with WCETs for each task and a NEVER set specifying the mutually exclusive tasks. Similar to [24], we then con sider all possible paths. For a given set of values of the conditionals, a particular path through the CDFG is defined (note that we assume that all conditionals controlling alternative executions are calculated by the beginning of each iteration of the CDFG) For this set of ....

R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Transactions on CAD/ICAS, Vol. 10, No. 1, January, 1991.

....by [27] It has been used and in systems like HAL [74] Other Scheduling Techniques: Scheduling is a very well studied and understood problem with many solutions and methodologies. Path based scheduling is another interesting algorithm which addresses the scheduling of control flow graphs [80]. Trace driven scheduling and percolation scheduling have also been proposed [75] Pipelining and Retiming: The topics of pipelining and retiming are not directly related to this thesis. That is why we do not go into the details of this methodology of optimizing throughput. SEHWA [26] was among ....

....allowable such that the likelihood of meeting the final design objectives does not change. Another major challenge being faced by the design community is the unpredictability uncertainty associated with estimation of cost functions. For example most scheduling algorithms in high level synthesis [80], 27] assume the knowledge of latency requirements for functional modules before scheduling. If this latency estimate is inaccurate the schedule potentially becomes invalid. Handling such uncertainties for upholding system level decisions such that costly design iterations are avoided is another ....

R. Camposano. " Path Based Scheduling for Synthesis". In HICSS90, pages 348--355, Jan 1990.

.... of attention because of its potential in significantly increasing the productivity of VLSI design [7] 8] 12] Experience has shown that HLS tools have better chance to be accepted in such specific application domains as digital signal processing (DSP) circuits [15] and control dominated circuits [6][18] Control dominated circuits are used in a wide variety of applications including protocol converters, network interfaces, etc. Therefore, automatic synthesis from a high level behavioral description of control dominated circuits is a worthy research. This work addresses storage ....

R.Camposano, "Path-Based Scheduling for Synthesis,"IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 85-93, Jan. 1991.

....[1] For this reason, most high level synthesis system either separate the two tasks or use heuristic approaches. Some systems perform module binding before scheduling, e.g. Caddy DSL [2] and BUD [3] some systems perform scheduling before module binding, e.g. Facet [4] DAA [5] YSC [6] HIS [7]. Combined heuristic scheduling and binding are performed in other synthesis systems, such as MAHA [8] ELF [9] Slicer Splicer [10] Chippe [11] Hal [12] and Genie S [13] It is important to remark that most of these approaches assume that each module is characterized a priori in terms of area ....

R. Camposano, "Path-based scheduling for synthesis," IEEE Transactions on CAD/ICAS, vol. Vol. 10, no. No. 1, pp. pp. 85-923, Jan. 1991.

....resource constraints of the schedule. The scheduling problem associates a control step (clock step) to each operation of a data flow graph such that the timing and resource constraints are met. Most of the previous work tries to solve the scheduling problem to meet the current design constraint [2], 4] 6] 7] They do not ensure any tolerance to uncertainties. We now illustrate the significance of slack in generating designs with robustness against uncertainties. Figure 2.1.1 illustrates a schedule with three additions in their respective control steps. Operation 2 is scheduled in step 1 ....

R. Camposano, "Path-based Scheduling for Synthesis", IEEE Transactions on CAD, Vol. 10, No. 1, pp. 85-93, 1990

....operator delays as multiple of clock periods. Chaining of data operations is considered in some cases as an extension of the basic scheme and not as the primary consideration. In any case, chaining of control operations with data operations is rarely considered. Path Based Scheduler [CaBe90] Cam91] was the first attempt to address these requirements. It works with Control Flow Graph (CFG) instead of Data Flow Graph (DFG) builds all possible control paths, schedules each of them separately following the AFAP strategy, and finally merg 72 es all different paths into one Finite State ....

.... how multiple paths are traversed, and how the loops are handled. In the sixth section the state marking rules are discussed, and in the seventh results of comparison of different scheduling approaches are presented. 5.2. Related work Path Based Scheduling (PBS) was introduced by [CaBe90] Cam91] as a mechanism to meet these scheduling requirements. In order to meet the first requirement, the PBS works with the control flow representation of behavior rather than the data flow representation used by earlier schedulers. Secondly, the problem of scheduling is formulated as a problem of ....

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R. Camposano, "Path-Based Scheduling for Synthesis", IEEE Transactions on Computer-Aided Design, Vol. 10, No. 1, pp. 85-93, January 1991.

....introduced in section 1.1. In summary, the scheduling scope includes: operand dependencies, controldependent behavior, sequential behavior and constraints, hardware resource constraints, repeating behavior, completeness and quality. Heuristic scheduling techniques are by far the most common [22][25] 44] 45] 58] 68] 71] 104] 109] 110] 121] 132] 133] 134] All heuristics, and in fact all scheduling techniques, address operand dependencies. If a scheduling technique only considers operand dependencies, then it only schedules data flow graphs, DFGs. Within the DFG paradigm, there is ....

R. Camposano, "Path-Based Scheduling for Synthesis", IEEE Trans. CAD/ ICAS, pp. 85-93, Jan. 1991.

....The priority of the operations is considered by the order the operations are scheduled. Since the above mentioned methods do not deal with loops or branches they are used to schedule operations inside such constructions. Path Based Scheduling (PBS) also called As Fast As Possible (AFAP) [Cam90] processes loops and branches and maps the operations to the control states in such a manner that the best schedule is found independently for every possible paths of the corresponding CFG. The computed schedules are overlapped by Proc. DMTCS CATS 99, Springer DMTCS, Auckland, Jan. 1999 3 ....

R. Camposano, "Path-Based Scheduling for Synthesis", IEEE Trans. on CAD, Vol. 10, No. 1, pages 85-93, 1991

....done in order to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7]. In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

....to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7] In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

[Article contains additional citation context not shown here]

R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Transactions on Computer-Aided Design, 10(1), January 1991.

....the degree of parallelism as much as possible within the given explicit and implicit constraints. Wellknown approaches which seem well suited at first sight could not be used directly to solve our scheduling problem [3] We have checked particularly Camposano s path based scheduling approach [4]. However the flag processing and the subroutine mechanism are specific to our scheduling problem and cannot be solved using this algorithm. Other scheduling techniques are mainly dataflow oriented [5] Our approach has some similarities with trace scheduling [6] and takes essential care of the ....

R. Camposano, Path based Scheduling for synthesis, IEEE Trans. on CAD, Vol.CAD10, Jan.91, pp.85-93

....done in order to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7]. In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

....to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7] In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

[Article contains additional citation context not shown here]

R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Transactions on Computer-Aided Design, 10(1), January 1991.

....done in order to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7]. In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

....to exploit parallelism in the schedule. However, as mentioned earlier the available blocks are highly preferred for those operations. Our method uses the idea of producing schedules for individual paths within a DFG. A similar scheme is used by other path based scheduling techniques [6, 7] In [6] each possible path is scheduled independently in an optimal fashion. Then the schedules for each path are overlapped, again in an optimal way. To allow the optimal scheduling of all execution paths, operations may be scheduled into several states. In our approach, one path of the input is ....

[Article contains additional citation context not shown here]

R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Transactions on Computer-Aided Design, 10(1), January 1991.

....task, the timing resolution is too low to be used for high performance design. Many improved timing models that specify the timing information in absolute time have been proposed. Among these models, the worst case delay model is commonly used to represent the timing behavior of operations [2], 15] 16] With this model, operator chaining can be used to minimize the slack time in each control step. However, the model usually leads to overestimated delays for most operator chains since it ignores the fact that the worst case delay of a whole operator chain is usually smaller than the ....

R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. Computer-Aided Design, vol. 10, pp. 85--93, Jan. 1991.

....control step corresponds to a basic machine cycle in a controlling FSM. 3 2.1 Dynamic Loop Scheduling Dynamic Loop Scheduling (DLS) 13] is a native VHDL scheduling algorithm optimised for the treatment of control flow dominated descriptions. It is based on the same principles of path scheduling [19] but significantly reduces the number of the generated paths and hence, the computation cost. DLS has been implemented and integrated with the high level synthesis tool, AMICAL [12] The main representation used by DLS is a control flow graph (CFG) 20] This kind of representation is ....

Camposano R., Path-Based Scheduling for Synthesis, IEEE T. CAD, Vol 10(1), pp85-93, January 1991.

....or VLIW compilers [1] typically use list scheduling [2] and force directed scheduling [3] or their variants for resource constrained and timing constrained scheduling. Relative scheduling [4] has the additional capability of scheduling operations with undeterministic delay. Pathbased scheduling [5], percolation scheduling , and trace scheduling exploits parallelism beyond the basic blocks. The phase coupling problem between the HLS subtasks has been noted in several systems and their solutions are to solve all the subtasks simultaneously with an ILP formulation. Among them are the work by ....

R. Camposano. Path-Based Scheduling for Synthesis. IEEE Transaction on CAD/ICAS, Vol. 10, No.1, January, 1991.

....to reason on predicate expressions involving arithmetic inequalities. Preliminary experimental results confirm its effectiveness. 1 Introduction False path analysis is an activity with application in a variety of computer science and engineering domains like for instance high level synthesis [1], 2] worst case execution time estimation [4] 5] 6] and software testing [8] Path based scheduling proposed in [1] considers all execution instances (control paths) The scheduling results can be further ameliorated by introducing the false path analysis technique described in [2] ....

.... 1 Introduction False path analysis is an activity with application in a variety of computer science and engineering domains like for instance high level synthesis [1] 2] worst case execution time estimation [4] 5] 6] and software testing [8] Path based scheduling proposed in [1] considers all execution instances (control paths) The scheduling results can be further ameliorated by introducing the false path analysis technique described in [2] Identification and elimination of false paths leads in a smaller number of control states, increased resource sharing in terms of ....

R. Camposano, "Path-based scheduling for synthesis", IEEE Trans. CAD, vol. 10, no. 1, pp. 85-93, 1991

....can tremendously simplify the use of the synthesis system because users can describe the functionality of the intended design with any language constructs or writting styles and still obtaining the same synthesized hardware. Traditional representations, such as CDFG [10, 12] VT [11] and CF DFG [3], satisfy the completeness property by encoding the input description into the representation in a one to one mapping manner. In other words, each language construct in the description is realized with a particular topology of nodes in the representation. For example, a VHDL[18] description can be ....

....nodes in the representation. For example, a VHDL[18] description can be compiled into a CDFG by mapping computations in a basic block to nodes in a data flow graph, and a conditional constructs to a control nodes [10, 12] Similar mappings from VHDL to CFG and from ISPS [1] to VT can be found in [3, 4, 11, 16]. Although these representations shown to be efficient, they lack the uniqueness. Since there exists a one to one correspondence between the constructs of input descriptions and the schema for the internal representation, different descriptions would result in different representation. The ....

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R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Trans. CAD, Vol.10, no.1, pp.85-93, Jan. 1991.

....(one adder and one comparator) produces designs with three states for Description3, and four states for Description4, as shown in Figure 1(b) Description4 requires an additional state because the value of variable X is computed twice. Some algorithms, such as the Path based Scheduling [4], try to minimize the impact of nested conditions by considering all possible paths in the description. In these algorithms, operations are scheduled according to the dependency in the Control Flow Graph (CFG) where nodes represent assignment or conditional statements and edges represent the ....

.... an adder and a multiplier, would produce a design with two states for the description in Figure 2(a) and three states for the description in Figure 2(b) Thus, results obtained with the path based scheduling algorithm depend on the ordering of operations in the description, as mentioned in [4]. The syntactic variation in the description can be minimized by applying a few transformations on the input description. Although many synthesis systems use transformations [1, 17] on their internal representation, these transformations do not try to reduce the impact of syntactic differences in ....

[Article contains additional citation context not shown here]

R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Trans. CAD, Vol.10, no.1, pp.85-93, Jan. 1991.

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R. Camposano. Path-Based Scheduling for Synthesis. IEEE TCAD, 10(1):85--93, January 1991.

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R. Camposano, "Path-based scheduling for synthesis, " IEEE Transactions on Computer-Aided Design, vol. CAD-10, pp. 85--93, January 1991.

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R. Camposano, "Path-based scheduling for synthesis," IEEE Trans. on Computer-Aided Design, vol. CAD-10, pp. 85--93, Jan. 1991.

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R. Camposano, "Path-Based Scheduling for Synthesis," IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, vol. 10, no. 1, pp. 85--93, Jan 1991.

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