M. Potkonjak, S. Dey and R. Roy," Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints," IEEE Transactions on Computer -Aided Design, 14(5):531-546,1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....improve controllability and observability by generating design solutions with the minimal number of loops, the minimal sequential depth between input and output registers and the maximal number of registers directly connected to primary input output ports. Another approach proposed in [DEY94] and [POT95] consists in using high level transformations and an adhoc assignment process in order to synthesize RTL designs such that all loops can be opened using a minimal number of scan registers. In [FER96] the authors present allocation binding methods for minimizing the number of scan registers ....

POTKONJAK M., DEY S., ROY R., "Considering testability at behavioral level: use of transformations for partial scan cost minimizing under timing and area constraints", IEEE Trans. on CAD, pp531-546, 1995.

....Pre selected scan variables are assigned to registers in order to generate design solutions with a minimal number of loops, a minimal sequential depth between input and output registers and a maximal number of registers connected to primary input output ports. Another approach proposed in [2] and [3] consists in using high level transformations and an ad hoc assignment process in order to synthesize RTL designs such that all loops can be opened using a minimal number of scan registers. In [4] the authors present allocation binding methods for minimizing the number of scan registers required ....

Potkonjak M., Dey S., Roy R., "Considering testability at behavioral level: use of transformations for partial scan cost minimizing under timing and area constraints", IEEE Trans. on CAD, pp: 531-546, 1995.

....in order to solve these testability problems and to obtain easily SATPG testable structures. Experimental results are presented in the last section. Testability problems definition and related works Testability issues targeted in related works on High Level Synthesis for Testability (e.g. 2] [3], 4] are mainly sequential depth reduction, loops reduction, and the increase of I O registers. Their experimental results show that generated structures have higher fault coverage, shorter test generation time and comparable size when compared with designs synthesized for area only. But, most ....

M. Potkonjak, S. Dey,, R. Roy: "Considering Testability at Behavioral Level: Use of transformations for partial scan cost minimization under timing and area constraints", IEEE Trans on CAD, Vol. 14, n.5, May 1995, pp: 531--546.

....to guide the HLS process to the generation of easily SATPG testable structures (SATPG stands for Sequential Automatic Test Pattern Generation) Experimental results are presented in the section VI. II Related works The testability issues targeted by most of HLS for testability systems (e.g. 2] [3], 4] are mainly sequential depth reduction, loops reduction, and the increase of I O registers. Most of these works do not consider the other testability bottlenecks induced by reconvergences or module transparence properties [5] Furthermore, these works do not rely on testability measures. ....

M. Potkonjak, S. Dey, R. Roy: "Considering Testability at Behavioral Level : Use of transformations for partial scan cost minimization under timing and area constraints", IEEE Trans on CAD, Vol. 14, n.5, May 1995, pp: 531--546.

.... considering a predefined scheduling of the operations, such as for instance, Finite State Machines and Data Path descriptions [4, 6, 9, 14] At this higher abstraction level, testability is often considered as a parameter to drive the high level synthesis tasks, in particular scheduling [1, 8, 17]. In this case, testability is evaluated with the aim of generating an easily testable RT level architecture. A hierarchical approach is applied, relying on gate level test sets for each individual module, and planning the test application for all modules, based on the behavioral information. This ....

S. Dey, M. Potkonjak, and R. Roy. Considering testability at behavioral level: Use of transformations for partial scan cost minimization under timing and area constraints. IEEE Trans. on CAD/ICAS, 14(5):531--546, May 1995.

....phase by maximally reusing existing scan registers. Since the deflection operations need to be executed in addition to the original operations, they are added only when the performance and area of the design is not adversely affected. Application of more complex transformations is discussed in [34]. The overall effect is that synthesizing a testable data path from the transformed specification requires fewer scan registers than needed for the original specification. 3.5 The Effect of A Controller on Testability Most of the behavioral synthesis for test techniques concentrate on improving ....

M. Potkonjak, S. Dey and R. Roy," Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints," IEEE Transactions on Computer -Aided Design, 14(5):531-546,1995.

....phase by maximally reusing existing scan registers. Since the deflection operations need to be executed in addition to the original operations, they are added only when the performance and area of the design is not adversely affected. Application of more complex transformations is discussed in [17]. The overall effect is that synthesizing a testable data path from the transformed specification requires fewer scan registers than needed for the original specification. A behavior level controllability enhancement technique that focuses on control flow is presented in [18] A decision node ....

M. Potkonjak, S. Dey, and R. Roy, "Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints," IEEE Transactions on Computer-Aided Design, vol. 14, pp. 531--546, May 1995.

.... hot potato, to reduce the partial scan overhead for generating easily testable data paths was demonstrated [9] Recently, Potkonjak et al. demonstrated a high effectiveness of a transformation based approach for simultaneous optimization of testability and area under throughput constraints [22]. TRANSFROMING AND SCHEDULING LINEAR COMPUTATIONS FOR TESTABILITY Table 1 shows several design metrics of six different structures of the eighth order IIR Avenhaus bandpass filter [1] The filter is widely used benchmark in DSP and high level synthesis literature. The table compares various ....

M. Potkonjak, S. Dey, R. K. Roy, "Considering Testability at Behavioral Level: Use of Transformations for Partial Scan Cost Minimization Under Timing and Area Constraints", IEEE Transactions on CAD, Vol. 14, No. 5, pp. 531-546, 1995.

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