H.J. Wunderlich. Self-Test Using Unequiprobable Random Patterns, Proc. of FTCS-17, pp. 258-263, 1987  Home/Search   Document Not in Database   Summary   Related Articles   Check

....hard to detect faults [Konemann 91] Dufaza 91] Hellebrand 92] Venkataraman 93] The seeds and characteristic polynomials need to be stored on chip. 3. Weighted Patterns: Logic is added to bias the pseudo random patterns towards those that detect the hard to detect faults [Schnurmann 75] Wunderlich 87] Bardell 87] Pomeranz 92] Hartmann 93] Multiple weight sets are usually required for an acceptable test length [Wunderlich 88] The weight sets need to be stored on chip. This paper presents a new approach for augmenting an LFSR, or any other pattern generating circuit, to produce a ....

....the least hardware overhead for a given test length compared with the other methods. In many cases, the proposed method reduces the test length significantly more than the other methods while using much less hardware. Wunderlich proposed a generator of unequiprobable random tests (GURT) in [Wunderlich 87] that requires very little hardware overhead but is limited to only one weight set. Hartmann and Kemnitz proposed a method in [Hartmann 93] that uses a modified GURT structure to generate equiprobable patterns and weighted patterns using a single weight set with 5 possible weights 0,2 k , ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. of FTCS-17, pp. 258-263, 1987.

.... BMS87] the multi functional test registers for a test per clock scheme are somewhat more sophisticated [KMZ79, OWM87] If the fault coverage of random patterns is not sufficient, weighted random patterns may be applied by a test per scan scheme [WLEF89, StWu91] or by a test per clock scheme [Wu87, Brg189]. Even pseudo exhaustive test sets can be generated by both methods [HWH90, BCR83] Figure 1: Test per scan scheme In general, combinational circuits are not pseudoexhaustively testable, and deterministic test sets have to be applied if the circuit is not allowed to be segmented by test points ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th Int. Symp. Fault-Tolerant Computing, Pittsburgh 1987, pp. 258-263

....BIST do not always provide high enough fault coverage for a reasonable test length. There are two ways to solve this problem: modify the pattern generator, or modify the circuit under test. A pseudo random pattern generator can be modified by adding logic to weight the patterns [Schnurmann 75] Wunderlich 87] Pomeranz 92] map the patterns [Touba 95a, 95b, 96] Chatterjee 95a] or reseed the generator [Venkataraman 93] Hellebrand 95] Zacharia 95] The circuit under test can be modified by inserting test points [Eichelberger 83] or by redesigning it [Touba 94] Chiang 94] Chatterjee 95b] ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. ofFTCS-17, pp. 258-263, 1987.

....r.p.r. faults, and the other is to modify the circuit structure to increase the detection probability of the r.p.r. faults so that they are no longer r.p.r. i.e. eliminate the r.p.r. faults) The test pattern generator can be modified by adding logic to weight the patterns [Schnurmann 75] Wundefiich 87] Pomeranz 93] correlate the patterns [Paternas 91] map the patterns [Touba 95a, 95b, 96b] Chatterjee 95a] or reseed the generator [Venkataraman 93] Hellebrand 95a, 95b] Zacharia 95] For on chip generation, these approaches generally require significantly more overhead than modifying ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. ofFTCS-17, pp. 258-263, 1987.

....to switch between them which can result in a lot of overhead. In order to reduce the BIST overhead for weighted pattern testing, researchers have looked for efficient methods for on chip generation of weighted patterns. Wunderlich proposed a Generator of Unequiprobable Random Tests (GURT) in [Wunderlich 87] that requires very little hardware overhead but is limited to only one weight set. Hartmann and Kemnitz proposed a method in [Hartmann 93] that uses a modified GURT structure and described test pattern generators for the C2670 and C7552 benchmark circuits [Brglez 85] that require very little ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. of FTCS-17, pp. 258-263, 1987.

....[3] This is because some signals in the circuit may not be set to specific logic values using pseudo random vectors, making faults on those signals hard to detect. Weighted random patterns have been found to yield better fault coverage in circuits that contain such random pattern resistant faults [4 8]. In these approaches, the probability of obtaining a 0 or a 1 at a particular input is biased towards detecting random pattern resistant faults. Weighting the pseudo random patterns [7, 9] is done using counter based schemes [10,11] or performing bit fixing (pattern mapping) 12] The ....

....[13 17] However, test sequences with acceptable test length and fault coverage are obtained at the expense of area overhead required to store seeds. Also, the complexity of computation of the seeds [17] rapidly increases with the number of primary inputs. E#cient hardware pattern generators [6,8] often round o# optimal weights, hence producing patterns that are sub optimal for certain circuits. In sequential circuits, faults may need a biased internal state in addition to biased input values, making it more di#cult to obtain a good set of weights. Deterministic BIST techniques such as ....

H. J. Wunderlich, "Self-test using unequiprobable random patterns," Proc. Fault-Tolerant Computing Symp., pp. 258-263, 1988.

....[3] This is because some signals in the circuit may not be set to specific logic values using pseudo random vectors, making faults on those signals hard to detect. Weighted random patterns have been found to yield better fault coverage in circuits that contain such random pattern resistant faults [4 8]. In these approaches, the probability of obtaining a 0 or a 1 at a particular input is biased towards detecting random pattern resistant faults. Weighting the pseudo random patterns [7, 9] is done using counter based schemes [10,11] or performing bit fixing (pattern mapping) 12] The ....

....[13 17] However, test sequences with acceptable test length and fault coverage are obtained at the expense of area overhead required to store seeds. Also, the complexity of computation of the seeds [17] rapidly increases with the number of primary inputs. Efficient hardware pattern generators [6,8] often round off optimal weights, hence producing patterns that are sub optimal for certain circuits. In sequential circuits, faults may need a biased internal state in addition to biased input values, making it more difficult to obtain a good set of weights. Deterministic BIST techniques such as ....

H. J. Wunderlich, "Self-test using unequiprobable random patterns," Proc. Fault-Tolerant Computing Symp., pp. 258-263, 1988.

....the r.p.r. faults, and the other is to modify the circuit structure to increase the detection probability of the r.p.r. faults so that they are no longer r.p.r. i.e. eliminate the r.p.r. faults) The test pattern generator can be modified by adding logic to weight the patterns [27] 30] [37]; correlate the patterns [26] map the patterns [7] 33] 34] 36] or reseed the generator [18] 19] 38] For on chip generation, these approaches generally require significantly more overhead than modifying the circuit structure itself. This paper focuses on techniques for modifying the ....

H.-J. Wunderlich, "Self-test using unequiprobable random patterns," Proc. Symp. Fault-Tolerant Computing, 1987, pp. 258--263.

....seeds and characteristic polynomials that will generate tests for the hard todetect faults [9,14,21] The seeds and characteristic polynomials need to be stored on chip. 3. Weighted Patterns: Logic is added to bias the pseudo random patterns towards those that detect the hard to detect faults [12,18,19,22]. Multiple weight sets are usually required for an acceptable test length [23] The weight sets need to be stored on chip. This paper presents a new approach for augmenting an LFSR, or any other pattern generating circuit, to produce a desired fault coverage for a given test length. No storage of ....

....the least hardware overhead for a given test length compared with the other methods. In many cases, the proposed method reduces the test length significantly more than the other methods while using much less hardware. Wunderlich proposed a generator of unequiprobable random tests (GURT) in [22] that requires very little hardware overhead but is limited to only one weight set. Hartmann and Kemnitz proposed a method in [12] that uses a modified GURT structure and described test pattern generators for C2670 and C7552 which require very little hardware overhead. However, these methods are ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. of FTCS-17, pp. 258-263, 1987.

....BIST do not always provide high enough fault coverage for a reasonable test length. There are two ways to solve this problem: modify the pattern generator, or modify the circuit under test. A pseudo random pattern generator can be modified by adding logic to weight the patterns [Schnurmann 75] Wunderlich 87] Pomeranz 92] map the patterns [Touba#95a,#95b] Chatterjee#95a] or reseed the generator [Venkataraman#93] Hellebrand#95] Zacharia#95] The circuit under test can be modified by inserting test points [Eichelberger 83] or by redesigning it [Touba#94] Chiang#94] Chatterjee#95b] ....

Wunderlich, H.-J., "Self-Test Using Unequiprobable Random Patterns," Proc. of FTCS-17, pp. 258-263, 1987.

....a tester with a pin programmable architecture. Recent research in weighted random test generation has been pursued in two main directions. One focused on the approaches to generating weights and weighted random sequences [3, 4, 5, 6, 7] The other included applications to built in self test, e.g. [8, 9, 10]. The approach proposed in this paper is illustrated in Figure 1. Given a (scan based) circuit description, a set of target faults, and a set of functional or random patterns, faults are graded for detection using a sequential fault simulator. During this phase, the circuit is in it s functional ....

H.-J. Wunderlich. Self Test Using Unequiprobable Random Patterns. In Dig. Int. Symposium on FaultTolerant Computing, pages 258--263, July 1987.

....still required 25 65 of the patterns in the full ATPG test set. Complete fault coverage without CUT modifications and external test patterns can be achieved by using a BIST scheme containing a more sophisticated pattern generator. Examples of this approach are weighted random pattern generators [Wund87, BRGL89, StWu91], pseudoexhaustive pattern generators [Aker85, HWH90] and deterministic pattern generators [HRTW95, ToMc96, WuKi96, KiWu97, KiWu98, KiWu99] However, the price for obtaining complete fault coverage usually is a relatively large amount of additional silicon area for the sophisticated pattern ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th Int. Symp. on Fault-Tolerant Computing, IEEE, 1987, pp. 258-263

....2565 of the patterns in the full ATPG test set. Complete fault coverage without CUT modifications and external test patterns can be achieved by using a BIST scheme containing a more sophisticated pattern generator. Examples of this approach are weighted random pattern generators [11] 24][28], pseudo exhaustive pattern generators [1] 15] and deterministic pattern generators [13] 16] 17] 18] 26] 27] However, the price for obtaining complete fault coverage usually is a relatively large amount of additional silicon area for the sophisticated pattern generator. In [16] 17] a ....

H.-J. Wunderlich, Self Test Using Unequiprobable Random Patterns, Proceedings 17th International Symposium on Fault-Tolerant Computing, IEEE, 1987, pp. 258263.

....Various BIST architectures based on pseudo exhaustive, random, weighted random, and deterministic patterns have been developed in recent years. They offer different tradeoffs between the test length and the hardware overhead required to achieve complete or sufficiently high fault coverage [1, 2, 4, 8, 9, 10, 11, 14, 25, 27]. In this paper, we address weight generation for random pattern testing which can be used either for a built in test scheme [8,20,27] or for a built off test scheme [23, 24] Weighted random patterns may be applied to circuits where uniform pseudo random testing would lead to an ....

.... tradeoffs between the test length and the hardware overhead required to achieve complete or sufficiently high fault coverage [1, 2, 4, 8, 9, 10, 11, 14, 25, 27] In this paper, we address weight generation for random pattern testing which can be used either for a built in test scheme [8,20,27] or for a built off test scheme [23, 24] Weighted random patterns may be applied to circuits where uniform pseudo random testing would lead to an insufficient fault coverage. Such a case is shown in figure 1. On sabbatical leave from the University of Siegen, Part of this work has been ....

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H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th Int. Symp. Fault-Tolerant Comput., Pittsburgh 1987, pp. 258-263.

.... BMS87] the multi functional test registers for a test per clock scheme are somewhat more sophisticated [KMZ79, OWM87] If the fault coverage of random patterns is not sufficient, weighted random patterns may be applied by a test per scan scheme [WLEF89, StWu91] or by a test per clock scheme [Wu87, Brgl89]. Even pseudo exhaustive test sets can be generated by both methods [HWH90, BCR83] scan path CUT signature register pattern generator Figure 1: Test per scan scheme In general, combinational circuits are not pseudoexhaustively testable, and deterministic test sets have to be applied if the ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th Int. Symp. Fault-Tolerant Computing, Pittsburgh 1987, pp. 258-263

....instance, the scan chain consists of several 32 bit data registers, the LFSR should be of length L = 32 bits, too. This prevents linear dependencies even if far less than 2 32 patterns are applied. The pattern generator PG of figure 2 can also be implemented to produce weighted random patterns [BRGL89b, Wu87, StWu91], pseudo exhaustive patterns [Akers85, HWH90] or deterministic patterns [HELL92, ToMc96, WuKi96] All these different types of pattern generators are able to obtain complete coverage of all detectable faults, and the whole structure is easily implemented by some CAD tool which supports scan ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th In. Symp. Fault-Tolerant Comput., Pittsburgh 1987, pp. 258-263

....with registers R1 . R9, combinational logic blocks (CLB) and pipeline structures In a test per clock scheme, some system registers are enhanced such that in special test modes they generate patterns or compact test responses. Examples of these multi mode test registers are BILBO and GURT [8, 9]. A test per clock scheme has advantages with respect to test application time, delay testing and defect coverage, but it often requires a higher hardware overhead than the test per scan scheme. In order to obtain self testable circuits, test registers must be placed at appropriate positions ....

H.-J. Wunderlich, "Self Test Using Unequiprobable Random Patterns", in Proc. International Symposium on Fault-Tolerant Computing, 1987, pp. 258-263

....signals [BaMc86, Bard90, RaTy98] see figure 3) However, even uncorrelated random patterns cannot guarantee complete fault coverage if a circuit contains random pattern resistant faults. Several schemes have been proposed for detecting these faults by applying weighted random patterns [BRGL89b, Wu87, StWu91], pseudo exhaustive patterns [Akers85, HWH90] or deterministic patterns [Koen91, HELL92, HELL95, ToMc96, WuKi96, ZRTW96, KiWu97] Most of the deterministic schemes are designed for single scan path architectures. Multiple scan chains are addressed in the schemes of [Koen91] and [ZRTW96] which ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th In. Symp. Fault-Tolerant Comput., Pittsburgh 1987, pp. 258-263

....test length and the hardware overhead required to achieve complete or sufficiently high fault coverage. Various BIST architectures based on pseudo exhaustive, random, weighted random and deterministic patterns offering different trade offs between the two parameters have been developed in the past [1, 2, 4, 5, 8, 9, 14, 25, 26, 27]. This paper targets an efficient test per scan architecture combining pseudo random and deterministic BIST. Such a scheme is very attractive because of the moderate hardware overhead and the simplicity of the implementation. The LFSR required for test pattern generation can be synthesized ....

H.-J. Wunderlich: "Self Test Using Unequiprobable Random Patterns", Proc. 17th Int. Symp. Fault-Tolerant Comput., Pittsburgh 1987, pp. 258-263

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H.J. Wunderlich. Self-Test Using Unequiprobable Random Patterns, Proc. of FTCS-17, pp. 258-263, 1987

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H.J. Wunderlich, "Self Test Using Unequiprobable Random Patterns", International Symposium on Fault-Tolerant Computing, 1987

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H.J. Wunderlich, "Self Test Using Unequiprobable Random Patterns," in IEEE International Symposium on Fault-Tolerant Computing, 1987, pp. 258--263.

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H.-J. Wunderlich. Self Test Using Unequiprobable Random Patterns. In Dig. Int. Symposium on Fault-Tolerant Computing, pages 258--263, July 1987.

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