J. Duato, P. Lopez, F. Silla and S. Yalamanchili, "A high performance router architecture for interconnection networks", In Proceedings of the 1996 International Conference on Parallel Processing, Bloomington, August 1996.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....VC8 after .2nS. 3) VC8 successfully grabs the token after 0.75nS. Figure 8. Waveforms of an 8 stage asynchronous token circuit. b) FHt bundling Transfer Technique We can further improve the router performance by fully pipelined the external flow control by means of a wave pipelining scheme [29] and sufficient amount of buffers at both ends. The latter isolates the effect of the buffer management technique on the virtual channel switching from flow control. Currently, electrical interconnects are not capable of high speed operation, which requires the design of extemal flow control to be ....

J. Duato, P. Lopez, F. Silla, and S. Yalamanchili, "A High Performance Router Architecture for Interconnection Networks," Proceedings of the 25 th International Conference on Parallel Processing, 61-68 (1996).

....circuit switching the header flit is first routed to the destination reserving virtual channels along the path. When a path has been setup, data flits are pipelined along this path as in wormhole switching [7] Wave switching combines wormhole and circuit switching in the same router architecture [53]. 3.1.4 Deadlock Avoidance An important issue that must be addressed in the design of a routing algorithm is the possibility of deadlock. Deadlocks occur as a result of cyclic waits for resources, such as buffers or links. Various approaches can be used to deal with deadlock. A preemptive ....

Jos'e Duato, Pedro L'opez, Federico Silla, and Sudhakar Yalamanchili. A High Performance Router Architecture for Interconnection Networks. In Proceedings of the

.... as wormhole [23] or Virtual Cut Through (VCT) 24] are the most suitable ones to maximize the performance for this kind of traffic (high throughput, low average latency) As there is no single switching technique suitable for both kinds of traffic, a good trade off is to use a hybrid approach [25], where the most suitable switching technique is used for each kind of traffic: a connection oriented scheme for the multimedia flows, and a connectionless scheme for best effort messages. The selected connection oriented scheme is Pipelined Circuit Switching (PCS) due to factors as its ....

J. Duato, P. Lopez, F. Silla, and S. Yalamanchili, "A high performance router architecture for interconnection networks," in International Conference on Parallel Processing (ICPP), August 1996.

....were able to use faster channels, network performance would increase considerably because bandwidth would be allocated to messages that really need that bandwidth. In a previous paper, we proposed a new hybrid switching technique called wave switching as well as a router architecture supporting it [10]. Wave switching implements wormhole switching and circuit switching concurrently. By combining circuit switching, pre established physical circuits 1 and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for ....

....concurrently. By combining circuit switching, pre established physical circuits 1 and wave pipelining across channels and switches, it is possible to increase network bandwidth considerably, also reducing latency for communications that use pre established physical circuits. As shown in [10], wave switching is able to reduce latency and increase throughput by a factor higher than three if messages are long enough ( 128 flits) even if circuits are not reused. For short messages, wave switching can only improve performance if circuits are reused. In this paper, we propose two routing ....

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J. Duato, P. Lopez, F. Silla and S. Yalamanchili, "A high performance router architecture for interconnection networks," in Proc. 1996 Int. Conf. Parallel Processing, August 1996.

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J. Duato, P. Lopez, F. Silla and S. Yalamanchili, "A high performance router architecture for interconnection networks", In Proceedings of the 1996 International Conference on Parallel Processing, Bloomington, August 1996.

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