L. Benini, P. Siegel, G. De Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 32-40, 1994.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... separately, in general, implies more test time (due to separate test session) and more overhead (due to direct observation of each) Recently, the effect of controller design on power consumption has been explored in [ 15] The work of [3] uses special state assignments to reduce power, while [4] adds some combinational logic to the original controller to avoid inactive state transitions. to block the global clock and effectively turn off the inactive components in the datapath. 2 Background Two approaches can be taken to testing a controller datapath pair. The first approach is to ....

L. Benini, P. Siegel and G. DeMicheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits;' IEEE Design and Test of Computers, Dec. 1994.

....first case, the switching component of the power dissipation typically dominates that due to leakage. In event driven (reactive) circuits, instead, the leakage may represent the main fraction of the total power. In fact, the switching activity can be kept null by gating the clock during idle time [5, 6, 7], but the circuit still dissipates because of leakages. The main techniques developed so far to solve this problem rely on changing the device threshold during the periods of inactivity. The device conductance threshold is kept low during normal operations to maintain a good operating speed, while ....

P. S. L. Benini and G. D. Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits," IEEE Design & Test, pp. 32--40, December 1994.

....techniques to improve controller area or performance. The importance of state assignment is discussed in [DeMicheli et al. 1984] and [Devadas et al. 1988] among others. Recently, the effect of controller design on power consumption has been explored in [Landman and Rabaey 1995] The work of [Benini and DeMicheli 1994] uses special state assignments to reduce power, while [Benini et al. 1994] adds some combinational logic to the original controller to avoid inactive state transitions. For self testable designs based on BIST (Built In Self Test) research involving controllers focuses on test plan and test ....

....assignment is discussed in [DeMicheli et al. 1984] and [Devadas et al. 1988] among others. Recently, the effect of controller design on power consumption has been explored in [Landman and Rabaey 1995] The work of [Benini and DeMicheli 1994] uses special state assignments to reduce power, while [Benini et al. 1994] adds some combinational logic to the original controller to avoid inactive state transitions. For self testable designs based on BIST (Built In Self Test) research involving controllers focuses on test plan and test scheduling [Abadir and Breuer 1985] Kime and Saluja 1982] Jone et al. 1989] ....

Benini, L., Siegel, P., and DeMicheli, G. 1994. Automatic synthesis of gated clocks for power reduction in sequential circuits. IEEE Design and Test of Computers 11, 4 (Winter), 32--40.

.... separately, in general, implies more test time (due to separate test session) and more overhead (due to direct observation of each) Recently, the effect of controller design on power consumption has been explored in [15] The work of [3] uses special state assignments to reduce power, while [4] adds some combinational logic to the original controller to avoid inactive state transitions. to block the global clock and effectively turn off the inactive components in the datapath. 2 Background Two approaches can be taken to testing a controller datapath pair. The first approach is to ....

L. Benini, P. Siegel and G. DeMicheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, Dec. 1994.

....and should be given some attention, since the prediction circuitry may be on the critical path and, therefore, it may impact the performance of the optimized design. Fig. 7. Example of gated clock architecture. Another approach to RT and gate level dynamic power management, known as gated clocks [101] [103] provides a way to selectively stop the clock, and thus force the original circuit to make no transition, whenever the computation to be carried out at the next clock cycle is useless. In other words, the clock signal is disabled in accordance to the idle conditions of the logic network. ....

L. Benini, P. Siegel, and G. De Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits," IEEE Design Test Comput. Mag., vol. 11, no. 4, pp. 32--40, 1994.

....This is effective when it is known that the logic fed by the latch is not being utilized during the current clock cycle. This idea has been used in the functional aspects of logic design for a long time. Its utility in terms of power reduction is also known by now, but not completely exploited [1, 2]. This idea can be pushed further to achieve power savings that may not be possible through just the gating of existing latches registers. As an example, consider a two operation ALU which is used for either addition or shifting. This is typically implemented using an adder and a shifter, and then ....

L. Benini, P. Siegel, and G. De Micheli. Automatic synthesis of gated-clocks for power reduction in sequential circuits. IEEE Design and Test, December 1994.

....This is effective when it is known that the logic fed by the latch is not being utilized during the current clock cycle. This idea has been used in the functional aspects of logic design for a long time. Its utility in terms of power reduction is also known by now, but not completely exploited [1, 2]. This idea can be pushed further to achieve power savings that may not be possible through just the gating of existing latches registers. As an example, consider a two operation ALU which is used for either addition or shifting. This is typically implemented using an adder and a shifter, and then ....

L. Benini, P. Siegel, and G. De Micheli. Automatic synthesis of gated-clocks for power reduction in sequential circuits. IEEE Design and Test, December 1994.

....is not subject to all these restrictions: it can be applied to any sequential specification. A consequence of its wider scope of usability, however, is that computational kernel extraction may be less scalable to very large sequential components. Automated extraction of clock gating logic [18] [22] is based on the observation that a sequential component can, under some input conditions, be unobservable or it may not react to input changes. In these cases, the circuit is idle and power can be saved by stopping its clock. This is done by creating a clock gating function that stops the ....

L. Benini, P. Siegel, and G. De Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits," IEEE Des. Test Comput., vol. 11, pp. 32--40, Dec. 1994.

....responsibility of the designer to find the conditions that disable the clock. Some attempts have been made to automate the generation of signals that can be used to gate the global clock. In [1] a Precomputation based approach has been described that focuses mainly on data path circuits, while in [2] the authors have described a method to generate gated clocks for systems described as finite state machines. Our previous work [2] exploits the concept of self loop, an idle condition for a Moore machine. If the machine is in a self loop, the next state and the output do not change, therefore ....

....of signals that can be used to gate the global clock. In [1] a Precomputation based approach has been described that focuses mainly on data path circuits, while in [2] the authors have described a method to generate gated clocks for systems described as finite state machines. Our previous work [2] exploits the concept of self loop, an idle condition for a Moore machine. If the machine is in a self loop, the next state and the output do not change, therefore clocking the FSM only wastes power. Obviously, detecting self loop conditions requires some computation to be performed by additional ....

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L. Benini, P. Siegel and G. De Micheli, "Automatic synthesis of gated clocks for power reduction in sequential circuits " IEEE Design and Test of Computers, pp. 32--40, Dic. 1994.

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L. Benini, P. Siegel, G. De Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 32-40, 1994.

No context found.

L. Benini, P. Siegel, G. De Micheli, "Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits, " IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 32-40, 1994.

No context found.

L. Benini, P. Siegel and G. De Micheli, \Automatic Synthesis of Gated Clocks for Power Reduction in Sequential Circuits," IEEE Design and Test of Computers, pp. 32-40, Dec. 1994.

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