Jonathan T.-Y. Chang and E. J. McCluskey, "Detecting Delay Flaws By Very-Low-Voltage Testing", Proc. International Test Conference, 1996. Home/Search Document Details and Download
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Resistive Bridge Fault Modeling, Simulation and Test Generation - Sar-Dessai, al. (Correct)
....circuit for different test vectors that excite the fault, along with the maximum detectable resistance R bmax at node Z for two different values of V DD . We have chosen 1. 2V for lowvoltage simulation because it is 2 V tn , where V tn is the device threshold of the NMOS device) in the VLV range [30]. An X in the table means that the fault is undetectable) For this circuit, simulation was done for bridging resistance from 0 to 6000W. Table 1. Maximum detectable resistance vs. V DD for Figure 8. Test vector A1B1A2B2 R bmax at V DD =3.3V R bmax at V DD =1.2V 0 0 1 1 2000W 6000W 1 1 ....
J. T.-Y. Chang and E. J. McCluskey, "Detecting Delay Flaws by Very-Low-Voltage Testing," Proc. Int. Test Conf., 1996, pp. 367-376.
Defect Detection Capability of Delay Tests for Path Delay Faults - Chakravarty (1996) (Correct)
....sometimes referred to as ac tests[17, 29] To detect defective ICs, ICs should be subjected to a variety of tests. A reasonable test suite will inlcude logic testing, at speed testing and I DDQ testing[17, 29] There is an ongoing study to ascertain the usefulness of including low voltage testing[2]. Recent empirical studies[17, 29] show that at speed tests detect many defective ICs that are missed during logic and I DDQ testing. Simulation studies also support this claim[2] Here we ask ourselves the question: are the existing methods good enough to detect defects that causes faulty dynamic ....
....and I DDQ testing[17, 29] There is an ongoing study to ascertain the usefulness of including low voltage testing[2] Recent empirical studies[17, 29] show that at speed tests detect many defective ICs that are missed during logic and I DDQ testing. Simulation studies also support this claim[2]. Here we ask ourselves the question: are the existing methods good enough to detect defects that causes faulty dynamic logic behaviour Similar questions can be asked for logic and I DDQ tests. We do not address those issues here. Currently, various techniques are used to compute at speed tests. ....
J. Chang, E. McCluskey, "Detecting Delay Flaws by Very-Low-Voltage Testing," IEEE International Test Conference, pp. 367-376, 1996.
Testing for Tunneling Opens - Li, McCluskey (2000) (3 citations) Self-citation (Mccluskey) (Correct)
....temperature and voltage burn in. Five failure modes are discussed as follows. 1) Threshold voltage shift is caused by hot carrier effects or process variation. This failure mode causes the circuit delay to increase significantly at very low voltage and therefore can be detected by VLV testing [Chang 96a] This failure mode could also cause the background leakage current to increase and hence be detected by I DDQ testing. Voltage burn in is effective in accelerating the hotcarrier injection effect because the electrons are accelerated to a higher energy as the V DD increases [Hnatek 95] Leblebici ....
....93] 2) Gate oxide shorts are caused by defective gate oxide. One simple model of this failure mode is a resistive short (between transistor gate and source or drain) which can cause excessive I DDQ current. It has been shown that VLV testing is effective in detecting gate oxide shorts [Chang 96a] Burn in is also effective in screening this failure mode because high temperature and high voltage accelerate the oxide degradation. 3) Metal shorts are unexpected shorts between metal wires. This failure mode may cause high I DDQ and it may also cause circuit delay to increase significantly ....
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Chang, J. and E.J. McCluskey, "Detecting Delay Flaws by Very-low-voltage Testing," Proceeding of International Test Conference, pp.367-376, 1996.
SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs - Chang, McCluskey (1997) (1 citation) Self-citation (Chang) (Correct)
....2 1. INTRODUCTION SHOVE testing aims at screening early life failures and intermittent failures so that we can improve the quality level of CMOS ICs at low cost. In conjunction with other testing techniques, such as IDDQ testing [Levi 81] and Very Low Voltage (VLV) Testing [Hao 93] Chang 96a] Chang 96b] we can ensure CMOS ICs quality without performing burn in. During SHOVE, test sets, such as single stuck at or pseudo stuck at test sets, are run at higher than normal supply voltage for a short period. Some defects occurred after SHOVE can only be detected by functional tests and some can ....
Chang, J.T.Y. and E.J. McCluskey, "Detecting Delay Flaws by Very-Low-Voltage Testing," Proc. 1996 IEEE ITC, Washington, DC, pp. 367-376, Oct. 20-24, 1996.
Modeling and Simulation of Time Domain Faults in.. - Júnior.. (Correct)
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Jonathan T.-Y. Chang and E. J. McCluskey, "Detecting Delay Flaws By Very-Low-Voltage Testing", Proc. International Test Conference, 1996.
The Application of a Square-Wave Supply Voltage to Detect.. - Vermaak, Kerkhoff (2002) (Correct)
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Chang, T.Y.J., and E.J. McCluskey, " Detecting Delay Flaws by Very-Low-Voltage Testing," in Proc. of International Test Conference, 1996, pp. 367-376
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