T. Filkorn, "A method for symbolic verification of synchronous circuits," in Proceedings of 10th IFIP Symposium on Computer Hardware Description Languages (CHDL'91), 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....has characteristic function: #R (#s) # S #(# q,#s) Systems with over 10 states have been analyzed by this method [Burch et al. 1990b] far larger than could ever be analyzed using explicit state graph methods. A number of refinements have been proposed to speed convergence [Burch et al. 1990a; Filkorn 1991] and to reduce the size of the intermediate OBDDs [Coudert et al. 1990] Unfortunately, the system characteristics that guarantee an efficient OBDD representation of the transition relation do not provide useful upper bounds on the results generated by symbolic state machine analysis. For ....

Filkorn, T. 1991. A method for symbolic verification of synchronous circuits. Computer Hardware Description Languages (Marseilles, April), IFIP, pp. 229--239.

....have no indication that the specification is complete. In the conclusion we explain how our work solves these problems. The analysis we perform compares the two models and tries to identify dissimilarities. It is therefore related to tautology checking of finite state machines 4 as is done in [10]. However the method in [10] is suggested as an alternative to model checking and not as a complementary method. The rest of this paper is organized as follows. Section 2 gives the necessary background. Section 3 describes the comparison criteria and the method for their use. Section 4 ....

....specification is complete. In the conclusion we explain how our work solves these problems. The analysis we perform compares the two models and tries to identify dissimilarities. It is therefore related to tautology checking of finite state machines 4 as is done in [10] However the method in [10] is suggested as an alternative to model checking and not as a complementary method. The rest of this paper is organized as follows. Section 2 gives the necessary background. Section 3 describes the comparison criteria and the method for their use. Section 4 exemplifies the different criteria by ....

T. Filkorn. A method for symbolic verification of synchronous circuits. In D. Borrione and R. Waxman, editors, Proceedings of The Tenth International Symposium on Computer Hardware Description Languages and their Applications, IFIP WG

....if W also satisfies the first requirement, which is equivalent to S 0 Z = Thus, the difference between forward and reverse reachability analysis is that the transition relation is reversed, and the roles of S 0 and Z 0 are swapped. Reverse reachability analysis has been studied by Filkorn [24], and it can be viewed as a generalization of a earlier methods for finding equivalent states in finite state machines [26, 32] In some cases, an invariant can be computed much more quickly with reverse reachability analysis than forward, even if both methods compute the same invariant. As an ....

....used. If the goal is to produce a verification tool that can be used with a minimum of training and without expert assistance, then full automation is of paramount importance. The power of the methods described here could not be used fully in such a verification tool. Other more automatic methods [1, 24, 34] might be more appropriate in this situation. Although fully automatic verification methods have become much more powerful in the last several years, there are still severe restrictions on the size of the circuits to which they can be applied. Our empirical results suggest that a small amount of ....

T. Filkorn. A method for symbolic verification of synchronous circuits. In Proceedings of the Tenth International Symposium on Computer Hardware Description Languages and their Applications, 1991.

....components and circuits to be used. Hardware description has been extensively studied. Languages such as CIRCAL, ELLA, HOL, LCF LSM, RTL, temporal logic, VHDL and many others have been used to specify and analyse hardware. The literature on this subject is vast; a few selected references are [3, 9, 11 13, 19, 20]. An interesting foil to the work reported in this paper is [24] which uses occam to specify and simulate logic circuits. In common with all such approaches, the goal of the work reported in this paper is to allow digital logic designs to be specified and analysed before actually building ....

Filkorn, T.: `A Method for Symbolic Verification of Synchronous Circuits', Proc. Computer Hardware Description Languages and their Applications IX, pp. 229--239, North-Holland, Amsterdam, NL, 1991.

....basis of numerous verification techniques such as model checking, input output equivalence, language containment, reachability analysis etc. Significant effort has therefore been spent on improving its practical performance, and towards tackling the state explosion problem using symbolic methods [2, 4, 5, 6, 12, 14]. In this paper, we describe the relative advantages of our symbolic state space representation in comparison to the standard deterministic finite state automaton (DFA) representation of sequential systems. Potentially, these advantages can be exploited in areas other than formal verification. ....

....2 NA 0.3 0.3 Counter 4 NA 0.3 0.3 Counter 8 NA 0.4 2.7 Counter 16 21 0.8 Counter 32 66 3.9 Counter 64 300 30.7 Table 2: Results for Counter Circuits some property, and work backwards implicitly through the transitions. In terms of other techniques based on symbolic backward traversal [6, 12], we have found a strong similarity between them and our LIF based method of checking I O equivalence. In fact, an implicit breadth first version of our LIF equality checking algorithm is operationally the dual of Filkorn s method based on computing non equivalent classes of states [6] However, ....

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T. Filkorn. A method for symbolic verification of synchronous circuits. In D. Boorione and R. Waxman, editors, Proc. 10th Int. Symp. on Comp. Hardware Description Lang. and their Applications. IFIP, North-Holland, April 1991.

....boolean functions. The main algorithm developed on this basis within the CHIC project is an algorithm for deciding equivalence of finite automata. It differs radically from the classical automata or graph theoretic algorithms and readily decides equivalence of automata with up to 2 2000 states [17]. Based on this algorithm, a new tool which is capable of dealing with digital circuit designs on a functional, or behavioural, level has been conceived, designed and implemented. This tool, the Circuit Verification Environment (CVE) 16, 18, 19, 20] has been extensively used for real ....

Thomas Filkorn. A Method for Symbolic Verification of Synchronous Circuits. In D. Borrione and D. Waxman (eds.) IFIP 10th Int. Symp. on Computer Hardware Description Languages (CHDL 91), 1991.

....systems synthesize complex sequential circuits which cannot be validated with simulation. On the other hand, a typical high level synthesis systems contains several 10K lines of code and such its correctness cannot be proven. Our approach exploits advances in symbolic state machine verification [6, 8]. With recent improvements of the system described by Filkorn in [8] we could verify sequential circuits with up to 260 binary state variables. The basic idea of this paper is to interpret the original high level specification, usually in behavioral VHDL [14] as a finite state machine and to ....

....with simulation. On the other hand, a typical high level synthesis systems contains several 10K lines of code and such its correctness cannot be proven. Our approach exploits advances in symbolic state machine verification [6, 8] With recent improvements of the system described by Filkorn in [8] we could verify sequential circuits with up to 260 binary state variables. The basic idea of this paper is to interpret the original high level specification, usually in behavioral VHDL [14] as a finite state machine and to verify with algorithmic methods that the original finite state machine ....

Th. Filkorn. A method for symbolic verification of synchronous circuits. In D. Borrione and R. Waxman, editors, CHDL 91 - Computer Hardware Description Languages and their Application, pages 229-- 239, Marseille, France, April 1991.

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T. Filkorn, "A method for symbolic verification of synchronous circuits," in Proceedings of 10th IFIP Symposium on Computer Hardware Description Languages (CHDL'91), 1991.

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T. Filkorn. A method for symbolic verification of synchronous circuits. In D. Borrione and D. Waxman, editors, IFIP 10th Int. Symp. on Computer Hardware Description Languages (CHDL 91), 1991.

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