Peter J. Ashenden. The VHDL Cookbook. Technical report, University of Adelaide, South Australia, July 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....decomposed into sub designs and how those sub designs are interconnected. With VHDL, the function of a design is described using familiar programming constructs. VHDL allows a design to be simulated so that several design alternatives can be compared and tested before a hardware prototype is built [2, 5]. VSPEC is an extension of VHDL. It allows designs to be specified in a declarative fashion as opposed to the operational style of VHDL. With VSPEC, the desired characteristics of a digital circuit are described instead of a single design artifact exhibiting these characteristics. VSPEC does not ....

Peter J. Ashenden. The VHDL Cookbook. Technical report, University of Adelaide, South Australia, July 1990.

....best of our knowledge, the specifications are given in HOL, which is in our opinion not well adapted to processor specification. The other processors are rather complex and their proofs emphasize the usefulness of our specification and proof methodology. DP 32 is a processor described in VHDL in [5]. Its verification has raised one error in its implementation. This proof shows that our framework is able to specify, and then to prove, a processor starting from its VHDL description. A VHDL description style provable in our framework has been derived from its verification [4] AVM 1 [20] has ....

P. J. Ashenden. The VHDL Cookbook. Dept. Computer Science, University of Adelaide, South Australia, first edition, July 1990.

....model of the target system are studied. The next paragraphs present the design and the realization of the campaign. Finally, the experimental results are given and analyzed. 5. 1 Design of the campaign The target system is a model of a very simple 32 bits processor, the DP32 described in [19], for which two architectures, one behavioral and one structural, are available. The structural model, on the register transfer level, is depicted in Figure 5; it is mainly composed of a finite state control machine (Control FSM) an ALU, a program counter (PC) a register file and several buffers ....

P. J. Ashenden, The VHDL Cookbook, University of Adelaide, South Australia, Tech. Report, 1990.

....phase level, then to the microprogram level, and nally to the assembly instruction level [2] The overall proof took less than 4 minutes on a Sun IPC workstation. AVM 1 [32] has been proved at the same levels in 30 minutes. The DP 32 processor has been specied from its original VHDL description [4] and then veried with SVP in 8 minutes [3] A real processor called MTI, designed by CNET in France, has been veried from the microprogram level to the assembly level. Several errors have been found in its implementation. 1 [13] proposes a slightly dioeerent diagram to verify pipelined ....

P. J. Ashenden. The VHDL Cookbook. Public Domain, Dept. Computer Science, University of Adelaide, South Australia, rst edition, July 1990.

....best of our knowledge, the specifications are given in HOL, which is in our opinion not well adapted to processor specification. The other processors are rather complex and their proofs emphasize the usefulness of our specification and proof methodology.DP 32 is a processor described in VHDL in [4]. Its verification has raised one error in its implementation. This proof shows that our framework is able to specify, and then to prove, a processor starting from its VHDL description. A VHDL description style provable in our framework has been derived from its verification [3] AVM 1 [21] has ....

P. J. Ashenden. The VHDL Cookbook. Public Domain, Dept. Computer Science, University of Adelaide, South Australia, first edition, July 1990.

....and reusable description of even very complex digital systems. Unfortunately, structuring and partitioning across many design units will prevent from quickly analysing a single model because related information is widely distributed. A small example taken from the ALU of the DP32 processor [2] illustrates this restriction of reverse engineering (Fig. 1) Additionally, the designer has to configuration dp32 rtl test . use entity work.ALU 32(behaviour) architecture behaviour . result = null after Tpd; package dp32 types is constant unit delay: Time : 1 ns; entity ALU 32 is ....

P. J. Ashenden. The VHDL Cookbook. University of Adelaide, Australia, 1990.

....[43] frequent use of the DLX architecture as a benchmark example for different experimental purposes, e.g. performance analysis, simulation, verification, synthesis, etc. availability of already implemented variants of the DLX processor using different tools as VHDL [47] or GENESIL [56] e.g. [6, 10, 19, 40, 78] 41 This implementation of the DLX processor contains a five stage pipeline with a two phased clock, and its architecture includes 51 basic instructions (integer, logic, load store and control) All these instructions are grouped into 5 classes according to which the stage and phase ....

P. Ashenden: DLX VHDL Model; Department of Computer Science, University of Adelaide, Australia, November 1993.

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P.J. Ashenden: The VHDL Cookbook. University of Adelaide, South Australia, Technical Report, 1990

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Peter J. Ashenden, The VHDL Cookbook, Dept. of Computer Science, University of Adelaide, 1990

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