S.-S. Lim, S. Min, M. Lee, C. Park, H. Shin, and C. S. Kim. An Accurate Instruction Cache Analysis Technique for Real-Time Systems. In Workshop on Architectures for Real-Time Applications, 1994. Home/Search Document Details and Download
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Determining the Worst Case Instruction Cache Miss-Ratio - Sebek, Gustafsson (2002) (Correct)
....a correct function. Adding caches to a real time system is a non trivial task since the execution time will become variable depending if the executing instruction or accessed data is in the cache or not. Some methods have nevertheless successfully been able to make system with caches analyzable [2, 3, 4, 5, 6, 7], but they all aim at WCET analysis. To the best of our knowledge no one has tried to bound WCCMR, even if many of the WCET analysis algorithms with some modifications would be able to perform such analysis. The major difference between the adjacent work and our proposition is the simplicity of ....
Sung-Soo Lim, Sang Lyul Min, Minsuk Lee, Chang Park, Heonshik Shin, and Chong Sang Kim. An accurate instruction cache analysis technique for real-time systems. In Proceedings of the Workshop on Architectures for Real-time Applications, April 1994.
Cache Issues in Real-Time Systems - Basumallick, Nilsen (1994) (22 citations) (Correct)
....of accesses was due to the fact that there was a conditional statement in one of the loops, and the analysis considered as a worst case scenario that the condition always evaluated to true. Another technique that uses a graph theoretic analysis of the program has been described by Lim et al. in [8] to analyze the instruction cache. In this technique, based Cache Issues in Real Time Systems 4 Iowa State University, May 94 on an extension of the timing schema[12] a mapping is established between each statement at the source level and the sequence of memory blocks corresponding to the ....
Lim, Sung--Soo, Min, S.L., Lee, M., Park, C.Y., Bae, Y.H., Shin, H., & Kim, C.S. : #An Accurate Instruction Cache Analysis Technique for Real--Time Systems#, Proceedings of the Workshop on Architectures for Real-- Time Applications, International Symposium on Computer Architectures, Chicago, April 1994
Worst-Case Execution Time Analysis on Modern Processors - Nilsen, Rygg (1995) (6 citations) (Correct)
....that determining worst case execution paths for the targeted computing environments was not at all straightforward. And this paper summarizes our experience. Most of the other research that has been published to date focuses on only one aspect of the more complete problem. For example, references [1 3, 6 9, 11 13, 19, 23] discuss techniques for analyzing cache performance. Pipeline analysis for real time predictability has been reported in [4, 5, 10, 22, 24] To our knowledge, the only other paper to consider the relationships between programming and analysis techniques is [15] 8. Acknowledgments We thank the ....
S. Lim, S. L. Min, M. Lee, C. Y. Park, H. Shin and C. S. Kim, An Accurate Instruction Cache Analysis Technique for Real-Time Systems, IEEE Workshop on Architectures for Real-Time Applications, April 1994.
Issues of Advanced Architectural Features in the Design of a.. - Rhee (1994) (2 citations) Self-citation (Lim Min Park Shin Kim) (Correct)
....is known only after the worst case execution path has been found due to history sensitive nature of caches. This cyclic dependency, in many cases, yields a pessimistic estimation of WCETs [6] To rectify the problem resulting from the cyclic dependency, we again extended the timing schema [4]. We will briefly describe the technique in the following. In the proposed technique, associated with each statement is a set of atomic objects, each of which abstracts an execution path in the statement. Each atomic object consists of two sets of memory block addresses and an execution time ....
....references are known in a later stage of analysis. This framework allows us to rewrite the timing schema so as to accurately analyze the timing behavior of cache memories. A detailed discussion of the resultant timing schema is beyond the scope of this paper and interested readers are referred to [4]. However, it is worth mentioning that the resulting timing schema is very similar to the one given in the previous section and that the two timing schemas can easily be combined. 5 Conclusion In this paper, we explained the difficulty of accurately estimating the time bounds of programs in ....
S.-S. Lim, S. L. Min, C. Y. Park, K. Park, Heonshik Shin, and C. S. Kim. An accurate instruction cache analysis technique for real-time systems. To appear in the Workshop on Architectures for Real-time Applications, 1994.
History-based Schemes and Implicit Path Enumeration - Claire Burguire And (Correct)
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S.-S. Lim, S. Min, M. Lee, C. Park, H. Shin, and C. S. Kim. An Accurate Instruction Cache Analysis Technique for Real-Time Systems. In Workshop on Architectures for Real-Time Applications, 1994.
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