J. E. Smith and A. R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....1. INTRODUCTION Contemporary superscalar microprocessors rely on aggressive execution reordering mechanisms to maximize the number of instructions committed per cycle. One of the main dynamic instruction scheduling artifacts used in such datapath designs is the Reorder Buffer (ROB) [17], which guarantees the recovery to a precise state when interrupts occur. The ROB is also used to handle branch mispredictions. It is typically implemented as a circular FIFO queue with head and tail pointers. Entries are made at the tail of the ROB in program order for each of the co dispatched ....

Smith, J. andPleszkun,A., "Implementation of Precise Interrupts in Pipelined Processors", in Proc. of Int'l. Symposium on Computer Architecture, pp.36--44, 1985.

....because it did not handle exceptions. We thus implemented precise interrupts in DSS for exceptions, to attain correct timing and program behavior in DSS. There are several methods we could have used to implement precise interrupts, such as a reorder buffer, a history buffer, or a future file [21]. As do many current microarchitectures, we use a reorder buffer to simulate the timing effects of precise interrupts. As we described previously, DSS checks for exceptions after each instruction, and if one is found, it flushes all entries in the reorder buffer after the faulting instruction. ....

J. E. Smith and A. R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th International Symposium on Computer Architecture, pages 36--44, June 1985. 23

....loads or stores [129] Other thread level speculations proposals followed the Multiscalar work [61, 156] 2.4. 2 Handling speculative state Buffering speculative register state is well studied and supported in modern processors either in the form of checkpoints, history buffers, or future files [153]. Nearly all proposals for speculative execution discussed earlier use local buffers to store speculative updates to memory. Knight [86] used the confirm cache local to each processor to store uncommitted data. Herlihy and Moss [66] used a transactional cache to track and buffer speculative ....

....versioning cache [52] to perform memory disambiguation and store speculative memory updates. Gharachorloo et al. 45] used the processor reorder buffer to track speculatively issued loads and the coherence protocol to check for violations. Ranganathan et al. 143] used a history buffer [153] to store speculatively retired instructions. These two schemes do not update memory specu 59 latively. Gniady et al. 48] use a special buffer, the Store History Queue, to buffer speculative updates to memory. 2.4.3 Detecting violations Nearly all techniques discussed above that speculate on ....

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James E. Smith and Andrew R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 1985.

....of the most recently completed and pending assignments to each register, relative to the end of the known instruction sequence, regardless of which instructions have been issued or completed. 6] Figure 3. Reorder Buffer Reorder Buffer The reorder buffer was first proposed by Smith and Plezkun [5] as a method for providing precise interrupts in processors with out of order execution. Today this method is useful not only for exception and interrupt recovery, but also for recovering from branch mispredictions. Using this method, the in order state is kept in the register file, and the ....

....lookahead state[Figure 3] The architectural state is found by combining the register file and the ROB. Implementation of the ROB is straightforward with the use of a first in first out (FIFO) queue. The ROB also overcomes the main drawbacks of the History Buffer presented by Smith and Plezkun in [5]. The history buffer takes several cycles to restore the in order state to the register file, but the ROB leaves the in order state intact in the register file. Thus, after an exception the ROB can simply discard its contents after the faulting instruction and instruction fetching can continue. ....

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J. E. Smith and A. R. Pleszkun, "Implementation of precise interrupts in pipelined processors" In Proceedings of the 12th Annual International Symposium on Computer Architecture, pp. 36-44, June 1985.

....been shown that implementing diagonal registers is as easy as adding new ports to VRF. Many modern processors increase the number of ports in register file to boost their performance by a small amount. The new ports could serve an added function units or to improve the interrupt handling system [54]. The diagonal registers improve the performance of some two dimensional applications by at least 100 , and their cost is compensated by adjusting the driver circuitry of VRF and adding new bu#ers if necessary. In general, the 5 overhead of the diagonal registers found in the simulation can be ....

Smith, J. E., Pleszkun, A.R., "Implementation of precise interrupts in pipelined processors ", International Symposium on Computer Architecture Conference, 1985

....of future research. 5.2 Buffering speculative state To recover from an SLE misspeculation, register and memory state must be buffered until SLE is validated. Speculative register state. Two simple techniques for handling register state are: 1. Reorder buffer (ROB) Using the reorder buffer [35] has the advantage of using recovery mechanisms already used for branch mispredictions. However, the size of the ROB places a limit on the size of the critical section (in terms of dynamic instructions) 2. Register checkpoint: This may be of dependence maps (there may be certain restrictions on ....

J.E. Smith and A.R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 1985.

....show that the simple VLIW machine slightly outperforms the superscalar machine, while the VLIW machine with predicating achieves a significant speedup of 1.41x over the superscalar machine. 1 Introduction Current high end microprocessors exhibit good performance through superscalar techniques [9][10][12] A superscalar machine dynamically schedules instructions from an instruction window on a predicted control path to exploit instruction level parallelism (ILP) Speculative execution is essential for instruction scheduling so that the scheduler can exploit ILP beyond basic block boundaries. ....

....out of order execution machine with support for speculative execution. Register renaming is used to avoid output and antidependences. Reservation stations [12] are provided for each function unit to check operand availability and issue instructions in parallel. A reorder buffer [10] is used to maintain the correct machine state. With these mechanisms in conjunction with dynamic branch prediction, the superscalar machine fetches a single instruction stream and schedules instructions in the stream so that pipelines never stall. 3 W V 0 31 n c1 c2 1 1 1234 5678 0 E ....

J. E. Smith and A. R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors," In Proc. 12th Int. Symp. on Computer Architecture, pp.36-44, June 1985.

....execution was first implemented in the IBM 360 90 [Ande67] Later studies in the early 70s formalized the concept of out of order execution as in [Tjad70] Kell75] The concept was revisited and extended in the 80s [Weiss84] Patt85] None of these studies tackled the problem of exceptions. [Smit85] first presented hardware schemes to manage exceptions precisely. Two major renaming structures were introduced: the reorder buffer and the history buffer. The reorder buffer provides physical locations to store the result of each instruction. Results update the processor state in this scheme once ....

J. E. Smith and A. R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors", in Proceedings of the 12 th International Symposium on Computer Architecture, 1985..

....handlers. 2.1 Hardware Speculation Mechanisms Some out of order execution processors preserve precise exceptions by deferring the commits of speculative instructions. Memory and register modifications are buffered in their program order into a retirement structure called a reorder buffer [21]. Instructions in the buffer are not allowed to affect state until all older instructions have completed and committed. Checkpoint repair mechanisms [12] have also been proposed to periodically preserve state. At checkpoints, copies of the register file are made, while between checkpoints, lists ....

J. E. Smith and A. R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 1985.

....normal execution after processing the interrupt. The hardware must provide mechanisms that enable an interrupt handler to accomplish all these tasks. The way by which most processors make it possible for interrupt handlers to accomplish all these functions is by implementing precise interrupts [9, 3]. The definition of a precise interrupt is derived from execution on a sequential architecture. In a sequential architecture, instructions are issued serially. An instruction is allowed to run to completion before the next one is issued. If any instruction interrupts, the interrupt is reported ....

....so on. When all instructions in the buffer have been processed, the register file has been restored to the required, precise, state. Most of the out of order completion, precise interrupt schemes described in the literature, such as the futurefile, in order buffer and reorder buffer mechanisms [9] are based on the idea of keeping around multiple copies of any overwritten register. The precise state is recovered by the discarding all values written after the interrupting instruction, and restoring the register state from the remaining values. They basically differ in implementation cost and ....

J.E. Smith and A.R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 1985.

....Section 7 gives some directions for future research. 2. Background and related works The issue buffer is the hardware structure materializing the instruction window. Instructions wait in the issue buffer until they are ready to be launched to the execution units. Unlike the reorder buffer [14], instructions can be removed from the issue buffer soon after issuing, to make room for new instructions. The two main phases of instruction issue are the wakeup phase and the selection phase [11] The wake up phase determines which instructions have their data dependencies resolved. The ....

J.E. Smith and A.R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, 1985.

....All memory instructions are dispatched to the AP. The IQ allows the AP to execute ahead of the EP, providing the necessary slippage between them to hide the memory latency. Exceptions are kept precise by means of a reorder buffer, a graduation mechanism, and the register renaming map table [13, 28]. Other decoupled architectures [27] had chosen to steer memory instructions to both units to allow copying data from the load queue to registers. Since preliminary studies showed that such code expansion would significantly reduce the performance, we implemented dynamic register renaming, which ....

J.E. Smith, A.R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proc. of the 12th. Int. Symp. on Computer Architecture, June 1985, 36-44.

....several preceding branches. When speculation is performed, speculated instructions must be prevented from retiring their results when their control dependent branches are mispredicted. Hardware support identical to that used by speculative out of order issue designs can be used to accomplish this [13], 14] 15] IV. Details of a miss path scheduler The previous section introduced some of the hardware structures required for an MPS implementation. The data stored in the def use table and the reservation table are used to make scheduling decisions. This section details the requirements on ....

....in Section III B. If speculation is used, a mechanism is required to prevent incorrectly speculated instructions from retiring their results. A method that is well suited for a speculative miss path scheduler is a reorder buffer with a future file to supplement the architectural register file [13]. Slots are allocated in the reorder buffer in original program order (this is preserved by the scheduler and stored with the individual instructions in the cache) The central issue in speculating instructions is choosing which instructions to speculate, a decision that relies on predicting ....

J. E. Smith and A. Pleszkun, "Implementation of precise interrupts in pipelined processors," in Proc. 12th Ann. Int'l Symp. Computer Architecture, Boston, MA, June 1985.

....of order, the processor is able to tolerate some long latency operations including cache misses with almost no overall performance degradation. To find enough independent instructions, most processors employ sophisticated branch prediction mechanisms [11, 29] and allow speculative execution [19, 12], committing results only when the true outcome of a branch is known. However, limitations due to finite resources, data dependencies and imperfect branch prediction, render the processor unable to tolerate the latencies of some long latency operations. These operations are likely to degrade ....

James E. Smith and Andrew R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 17--19, 1985. IEEE Computer Society TCA and ACM SIGARCH. Computer Architecture News, 13(3), June 1985.

....and then updates the register file with the results in the original program order. Results are written to the register file in order by operating the reorder buffer in FIFO fashion. As entries in the reorder buffer reach the bottom of the FIFO, the completed results are written to the register file[3]. The organization of a reorder buffer in a superscalar processor is shown in Figure 1. Each decoded instruction is allocated an entry at the top of the reorder buffer. During allocation, the instruction s destination register identifier and a unique tag identifier for the instruction are entered ....

James Smith and Andrew Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 1985.

.... Floating Point Exceptions 157 cycle and retiring operations out of order the trapping hardware itself becomes more costly to implement and can itself add to the time needed to perform operations on ordinary floating point numbers [Hennessy and Patterson 1990; Hwu and Patt 1987; Johnson 1991; Smith and Pleszkun 1985; Sohi and Vajapeyam 1987] Hence, incorporating gradual underflow into a processor s arithmetic involves engineering tradeo#s that are becoming increasingly uncomfortable. Recently, one manufacturer has decreed that subnormal numbers will be supported on their processors only in a degraded mode ....

Smith, J. E. and Pleszkun, A. R. 1985. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture. IEEE Computer Society Press, Silver Springs, Md., 36--44.

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James E. Smith and Andrew R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th Annual International Symposium on Computer Architecture, pages 36--44, June 17-- 19, 1985.

....perform memory disambiguation at run time, thereby allowing loads and stores to bypass each other when advantageous. Storage conflicts in the original code are eliminated at run time by performing register renaming in the hardware [10] Register renaming is implemented by using a reorder buffer [19] associated with each register file. The reorder buffer provides the additional storage necessary to implement register renaming. For example, when an instruction is decoded, MATCH dynamically allocates a location in the reorder buffer for this instruction s result and the instruction s ....

J.E. Smith and A.R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors." Proceedings of the 12th Annual International Symposium on Computer Architecture (June 1985), pp. 36-44.

....movement into safe speculative execution, and thus a compiler alone cannot support the general movement of instructions above their control dependent branch. There are numerous hardware techniques that allow dynamic schedulers to safely move any instruction above its control dependent branch [15][21]. The basis of all these techniques is the inclusion of extra buffering in the hardware which holds the effects of the speculative operations 1 . The sequential state of the machine is defined as that machine state that is not a result of any speculative operation, and conversely, the ....

....superscalar processor with speculative execution support. The dynamic scheduler is functionally equivalent to our base superscalar machine. The dynamic scheduler fetches and decodes two instructions per cycle. It uses a total of 30 reservation station locations [28] and a 16 entry reorder buffer [21] to implement outof order execution with speculation, and it uses a 2048 entry, 4way set associative branch target buffer to predict branches. It has the same number of functional units as our statically scheduled machine, but since the dynamically scheduled machine uses reservation stations, it ....

J.E. Smith and A.R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proc. 12th Int. Symp. on Computer Architecture, pp. 36--44, June 1985.

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J. E. Smith and A. R. Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors," Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985.

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J. E. Smith and A. R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th pages 36--44, June 1985.

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J. E. Smith, A. Pleszkun, " Implementation of Precise Interrupts in Pipelined Processors," in International Symposium on Computer Architecture, pp. 36-44, June 1985.

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J.E. Smith and A.R. Pleszkun. Implementation of precise interrupts in pipelined processors. In 12th International Symposium on Computer Architecture, pages 36--44, June 1985.

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J.E. Smith, A.R. Pleszkun. Implementation of Precise Interrupts in Pipelined Processors. In Proc. of the 12th. Int. Symp. on Computer Architecture, June 1985, 36-44.

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J. E. Smith and A. R. Pleszkun. Implementation of precise interrupts in pipelined processors. In Proceedings of the 12th pages 36--44, June 1985.

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