P. A. Beerel, C. J. Myers, and T. H.-Y. Meng, Automatic synthesis of gatelevel speed-independent circuits, Tech. Rep. CSL-TR-94-648, Stanford University, Novermber 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....designed. Many methods have been proposed for the specification of asynchronous designs. Some, however, are restricted to the signal transition level, such as I nets [17] signal transition graphs [7] 16] change diagrams [26] asynchronous finite state machines [9] 22] 28] and state graphs [1]. Some languages do exist which abstract the behavior of the design, but they use non standard languages such as communicating sequential processes (CSP) 14] Occam [5] and Tangram [4] Each of these specification methods is also designed for a particular design style and synthesis methodology. ....

....can occur. The composition of two TEL structures S 0 = hN 0 ; A 0 ; E 0 ; R 0 ; # 0 ; first 0 ; last 0 i and S 1 = hN 1 ; A 1 ; E 1 ; R 1 ; # 1 ; first 1 ; last 1 i (i.e. S 0 op S 1 where op 2 f; k; jg) is defined as follows: zx y b c [8,12] a [3,10] Conjunctive (a) c c a b [1,4] a b [2,6] AND gate (c) xy z [2,4] a b c [2,6] y # zConflict (b) Figure 3.1. Examples of TEL structures. 22 N = N 0 [ N 1 A = A 0 [ A 1 E = E 0 [ E 1 R = R 0 [ R 1 [ fhx; y:e; y:l; y:u; y:bi j x 2 last 0 y 2 first 1 op = g # = # 0 [ # 1 [ f(e; e 0 ) j (e 2 E 0 e 0 2 E ....

P. A. Beerel, C. J. Myers, and T. H.-Y. Meng, Automatic synthesis of gatelevel speed-independent circuits, Tech. Rep. CSL-TR-94-648, Stanford University, Novermber 1994.

....= M rc . MTBDDs are an ideal way to represent this type of function [15] BDDs are constructed for each necessary row and column index, and stored in arrays r and c. The BDD for the i th column index is stored in c[i] and the BDD for the i th row index is stored in r[i] For example, r[3] represents the value 3 using a set of variables which indicate that it is a row index. Each augmented matrix is then transformed into a MTBDD. Figure 2.8 shows the algorithm used to accomplish the transformation. First, fi is initialized to FALSE. Then each matrix location is considered in ....

....circuit chosen. In a gC implementation, any state where the signal is enabled in the same direction or stable at the final value may be included. In a SC circuit, some of those states may need to be excluded to guarantee hazard freedom. The correctness constraints discussed here were developed in [3] for speed independent circuits and extended to timed circuits in [30] 3.3.1 gC cover violations In a gC implementation, the allowed growth regions include the remainder of the excitation space and the entire quiescent space for the corresponding signal transition. In other words, correct covers ....

Beerel, P. A., Myers, C. J., and Meng, T. H.-Y. Automatic synthesis of gate-level speed-independent circuits. Tech. Rep. CSL-TR-94-648, Stanford University, Novermber 1994.

....circuit chosen. In a gC implementation, any state where the signal is enabled in the same direction or stable at the final value may be included. In a SC circuit, some of those states may need to be excluded to guarantee hazard freedom. The correctness constraints discussed here were developed in [1] for speed independent circuits and extended to timed circuits in [14] In a gC implementation, the allowed growth regions include the remainder of the excitation space and the entire quiescent space for the corresponding signal transition. In other words, correct covers must satisfy the ....

P. A. Beerel, C. J. Myers, and T. H.-Y. Meng. Automatic synthesis of gate-level speed-independent circuits. Technical Report CSL-TR-94-648, Stanford University, Novermber 1994.

....and ORed together with the preceding initial cover (i.e. C = C 0 C 1 : Cm ) In order to create a valid timed circuit implementation, it is necessary to define the states a cover must include, may include, and may not include. The correctness constraints discussed here were developed in [1] for speed independent circuits and extended to timed circuits in [12] In a gC implementation, the allowed growth regions include all states in ES and QS for the corresponding signal transition. This covering constraint prevents the gate from being pulled up and down simultaneously or changing ....

....workstation with 32 Mbytes of memory. The sixth column of each table reports the runtime to translate the explicit representation of the state space to two BDDs. We compare the runtimes of our BDD synthesis method to a heuristic single cube algorithm [10] and to a general multi cube algorithm [1]. For each algorithm, we compare the runtimes for generating both a gC and a SC implementation. An entry of fail indicates that an algorithm did not complete due to limitations in time and space. The last two columns present the number of potential implementations for the entire circuit. This ....

P. A. Beerel, C. J. Myers, and T. H.-Y. Meng. Automatic synthesis of gate-level speed-independent circuits. Technical Report CSL-TR-94-648, Stanford University, Novermber 1994.

.... entrance constraint which says that a correct cover must only be entered through excitation region states, i.e. Theta (s; s 0 ) 2 Gamma s 62 C(u; k) s 0 2 C(u; k) s 0 2 ER(u; k) The definition of correct covers is based on the definition given for speed independent circuits in [2]. This definition differs slightly from the one in [2] in that QS(u; k) does not need to be a maximally connected set of states, but it is easy to show this condition is made redundant by the entrance constraint. Extending the proof for the speed independent case, it can be shown that these ....

.... only be entered through excitation region states, i.e. Theta (s; s 0 ) 2 Gamma s 62 C(u; k) s 0 2 C(u; k) s 0 2 ER(u; k) The definition of correct covers is based on the definition given for speed independent circuits in [2] This definition differs slightly from the one in [2] in that QS(u; k) does not need to be a maximally connected set of states, but it is easy to show this condition is made redundant by the entrance constraint. Extending the proof for the speed independent case, it can be shown that these conditions ensure when the specified timing assumptions are ....

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P. A. Beerel, C. J. Myers, and T. H.-Y. Meng. "Automatic synthesis of gate-level speed-independent circuits", November 1994. Submitted for publication in IEEE Transactions on Computer-Aided Design.

....Several speedindependent design techniques are based on the signal transition graph (STG) specification such as the work by Chu [17] and Meng [47] The work by Chu and Meng, however, often produce circuits that require large complex atomic gates. To address this problem, Beerel et al. [7] developed constraints to add to the synthesis method to produce implementations using only basic gates such as AND gates, OR gates, and C elements. Since then there has been some additional work in this area by Lin and Lin [42] and Kondratyev et al. 37] The primary advantage of quasi delay ....

....mapping techniques. In both of these approaches, timing analysis is applied only after synthesis to verify that hazards do not exist. If hazards are detected, delay elements are added to avoid them, degrading the reliability and performance of the implementation. Beerel et al. has shown in [7] that the more conservative speed independent model while resulting in somewhat larger circuits actually produces faster circuits compared with the timed circuits described in [38] This surprising result can be attributed to the fact that these timed circuits often need to have delay elements ....

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P. A. Beerel, C. J. Myers, and T. H.-Y. Meng. Automatic synthesis of gate-level speed-independent circuits. Technical Report CSL-TR-94-648, Stanford University, Novermber 1994.

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