K.D.Wagner, S.Dey: "High-Level Synthesis for Testability: A Survey and Perspective", Proc. Design Automation Conference 96, Las Vegas, June 1996, pp.131-136 Home/Search Document Details and Download
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An Integrated System-Level Design for Testability Methodology - Larsson (2000) (Correct)
....register (LFSR) and the response analyser as a multiple input signature register (MISR) A built in logic block observer (BILBO) is a register which can operate both as a test pattern generator and a signature analyser. However, the disadvantage of using BILBOs is the large area and delay penalty [Wag96]. An advantage of using the BIST technique is that tests are performed at speed. The technique also has a lower test application time compared to the scan technique. Since the BIST technique does not require any special test equipment, it can be used not only for production test, but also for ....
Kenneth D. Wagner and Sujit Dey, High-Level Synthesis for Testability: A Survey and Perspective, Proceedings of the Design Automation Conference, pp. 131-136, Las Vegas, June 1996.
TAO: Regular Expression based High-Level Testability.. - Ravi, Lakshminarayana, .. (1998) (4 citations) (Correct)
....them, full or partial scan based techniques [15, 16] are commonly used. However, the area and delay overheads incurred in scan based designs are not always small. High test application time is also an area of concern in such designs. More recently, DFT techniques at the RTL have been proposed [3, 7, 17, 18]. These approaches selectively apply a DFT enhancement to a circuit ignoring possible benefits from a judicious application of a combination of these techniques. For example, the DFT approaches in [3] and [7] are based solely on test multiplexer addition and partial scan, respectively. We are, ....
K. D. Wagner and S. Dey, "High-level synthesis for testability: A survey and perspective," in Proc. Design Automation Conf., pp. 131-- 136, June 1996.
Datapath Testability Improvement through ad hoc.. - Flottes Pires Rouzeyre (Correct)
....performs computation on data applied on data primary inputs. The controller sequences the normal flow of execution on the datapath. Even if the datapath is fully testable when considered in isolation, particularly if generated using a High Level Synthesis for Testability tool (see [1] and [2] for a survey) its testability can be strongly affected after connection to the control part. As a matter of fact, the controller implements only the normal flow of execution (system mode) As a consequence, the set of actual words on the control signals and the next state logic may limit the ....
K.D.Wagner, S.Dey,: High-Level Synthesis for Testability: a Survey and Perspective, Proc. 33rd ACM/IEEE Design Automation Conference, pp.131-136,
Alleviating DFT cost using testability driven HLS - Flottes, Pires, Rouzeyre (Correct)
....of some characteristics of the circuit, like performance and area. In order to mitigate these consequences, it has been proposed in the early 90 s to take into account testability at the beginning of design flow, namely during HLS. A survey of HLS for testability techniques can be found in [1], 2] A favorable step in HLS for solving testability problems is the register allocation binding phase. During this step a sufficient number of registers is determined for storing behavioral variables, and variables are assigned to accordingly. The large number of achievable solutions and the ....
K.D.Wagner, S.Dey "High-Level Synthesis for Testability: a Survey and Perspective", Proc. DAC, pp.131-136, 1996
TAO: Regular Expression based High-Level Testability.. - Ravi, Lakshminarayana, .. (1998) (4 citations) (Correct)
....them, full or partial scan based techniques [12, 13] are commonly used. However, the area and delay overheads incurred in scan based designs are not always small. High test application time is also an area of concern in such designs. More recently, DFT techniques at the RTL have been proposed [3, 14, 15, 16]. These approaches selectively apply a DFT enhancement to a circuit ignoring possible benefits from a judicious application of a combination of these techniques. For example, the DFT approaches in [3] and [14] are based solely on test multiplexer addition and partial scan, respectively. We are, ....
K. D. Wagner and S. Dey, "High-level synthesis for testability: A survey and perspective," in Proc. Design Automation Conf., pp. 131-- 136, June 1996.
A Design for Testability Technique for RTL Circuits Using.. - Indradeep Ghosh (1996) (4 citations) (Correct)
....the number of primitive elements in the circuit is reduced, thus making the problem size more tractable. In recent years, various behavioral and architectural schemes have been proposed to generate easily testable sequential circuits. These techniques may target BIST, scan or sequential ATPG [2]. However, while targeting a circuit for testing, the behavioral description is not available in many cases. Solving the problem at the gate level suffers from the problems mentioned above. Hence, in order to get the testability advantages of a higher level of abstraction, the RTL merits ....
K.D. Wagner and S. Dey, "High-level synthesis for testability: A survey and perspective," in Proc. Design Automation Conf., pp. 131-136, June 1996.
Non-Scan Design-for-Testability Techniques Using RT-Level.. - Dey, Potkonjak (1997) (3 citations) Self-citation (Dey) (Correct)
....RTlevel method was presented to generate self testable RT level data paths, using allocation and automatic test point selection to reduce the sequential depth from controllable to observable registers. A comprehensive survey of the behavioral and RTlevel test synthesis techniques can be found in [36]. Like the behavioral synthesis for testability techniques summarized above, all the existing RT level techniques are scan based and cannot generate testable data paths without the use of scan. C. Testability of Sequential Circuits The dependencies of the FF s of a sequential circuit are ....
K. Wagner and S. Dey, "High level synthesis for testability: A survey and perspective," in Proc. Design Automation Conf., June 1996, pp. 131--136.
Design for Testability Techniques At the Behavioral and.. - Dey, Raghunathan, Wagner (1998) (2 citations) Self-citation (Wagner Dey) (Correct)
....Test problems that cannot be fixed by lower level optimizations alone require additional design iterations, leading to increased design cycles. Thus, the benefits of high level design cannot be fully realized unless consideration of testability is also integrated into the high level design process [1]. A behavioral description contains an algorithmic specification of the design s functionality, and may contain little or no information about the design s cycle by cycle behavior or structural implementation. Behavioral synthesis tools typically compile a behavioral description into a suitable ....
K. D. Wagner and S. Dey, "High-level synthesis for testability: A survey and perspective, " in Proc. Design Automation Conf., pp. 131--136, 1996.
A Low-Redundancy Approach to Semi-Concurrent Error.. - Anna Antola Vincenzo (1998) (3 citations) (Correct)
No context found.
K.D.Wagner, S.Dey: "High-Level Synthesis for Testability: A Survey and Perspective", Proc. Design Automation Conference 96, Las Vegas, June 1996, pp.131-136
Design for Testability Reuse in Synthesis for Testability - Peter Bukovjan Meryem (1999) (Correct)
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K. Wagner and S. Dey. High-level synthesis for testability: a survey and perspectives. In Proceedings of the Design Automation Conference, pages 131--136, 1996.
Allocation for Testability in High-Level Synthesis - Bukovjan (2000) (Correct)
No context found.
K.D. Wagner and S. Dey. High-level synthesis for testability: a survey and perspectives. In Proceedings of the Design Automation Conference, pages 131--136, 1996.
An Incremental Approach for Test Scheduling and Synthesis.. - Harmanani, Hajar (2004) (Correct)
No context found.
K. Wagner, S. Dey, "High-Level Synthesis for Testability: A Survey and Perspective," in Proc. DAC, 1996.
Low-Cost Test For Core-Based System-On-A-Chip - Gonciari (2003) (Correct)
No context found.
K. D. Wagner and S. Dey, "High-Level Synthesis for Testability: A Survey and Perspective," in Proceedings ACM/IEEE Design Automation Conference (DAC), pp. 131--136, Association for Computing Machinery, Inc., June 1996.
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