J. Lu and S. Tahar "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS", Proc. IEEE 8 th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, Feb. 1998, pp. 368373.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....with our unique generic temporal lemma. Tahar in [18] proved the Fabric using MDG (Multiway Decision Graphs) He handles bigger automata and his proof is more automatic. However it is not reusable. Other approaches on the Fabric propose abstraction processes in order to alleviate the proof process [12] [8] Several comparisons have been studied in this field [17] 16] ....

J. Lu and S. Tahar. Practical Approaches to the Automatic Verification of an ATM Switch using VIS. In IEEE 8th Great Lakes Symposium on VLSI (GLSVLSI '98), pages 368--373, Lafayette, Louisiana, USA, Feb. 1998. IEEE Computer Society Press.

No context found.

J. Lu and S. Tahar "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS", Proc. IEEE 8 th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, Feb. 1998, pp. 368373.

No context found.

J. Lu and S. Tahar, "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, pp. 368-373. February 1998.

No context found.

J. Lu and S. Tahar, "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, pp. 368-373, February 1998.

No context found.

J. Lu and S. Tahar. "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, pp. 368-373. February 1998.

....behavior and structure of the lower level hardware modules and automated their verification. Jakubiec et. al [15] used it in their work based on the Coq proof system. Garcez et. al [11] has also verified some properties of the fabric using the HSIS model checking tool. More recently, Lu et. al [18] used the VIS tool [1] to verify relevant liveness and safety properties (described in CTL) on various abstracted models of the Fairisle fabric. In addition, they conducted equivalence checking between the behavioral and structural specifications of the submodules written in Verilog. The authors ....

....is automatic and the authors succeed in checking some important properties related to the circuit implementation. Yet, the adopted data abstraction (e.g. using 1 bit to represent 8 bit data width) for avoiding state explosion is not always applicable. The ATM verification performed by Lu et. al [18] using an automated ROBDD based tool, VIS, failed to complete the verification of even a very reduced model of the switch fabric through equivalence checking. 5 To overcome these drawbacks, we attempt to raise the level of abstraction of automated verification methods to that of interactive ....

[Article contains additional citation context not shown here]

J. Lu and S. Tahar, "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI (GLS-VLSI'98), Lafayette, Louisiana, USA, February 1998.

....ICA (Input Cell Available) and IWREN (Write Enable) signals. The other is address line polling. There are 32 physical devices which are accessed by 5 bit physical address and share the same ICA and IWREN signals. 4. VERIFICATION OF THE INPUT FIFO We used the same methods that we described in [7] to do the verification. We wrote the RTL description of the input FIFO in Verilog, with some minor changes on the model. The difference between the original model and our verification model was that we only used 16 bit datapath while the original design used either 16 bit or 8 bit datapath. In ....

....but VIS could not handle such big memory verification. Therefore, we verified the control circuits of the input FIFO excluding the memory. Such reduction is practical because usually the control circuit is the critical part in the verification. 4. 1 The Environment of the Input FIFO Similar to [7], we established an environment for the input FIFO, and the environment gives the inputs as random variables and defines registers as a default value. Figure 2 gives the code for the required environment. In Figure 2, lines 2 to 9 are inputs from transceiver board and the block of Micro cell ....

[Article contains additional citation context not shown here]

J. Lu and S. Tahar. "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, pp. 368-373. February 1998.

....it can be applied to verify the equivalence between an RTL design and its behavioral model. But the drawback of sequential equivalence checking is the socalled state space explosion problem [7] so that it is hard to be applied in a large design. To make use of sequential equivalence checking, in [8] we applied modular sequential equivalence checking on the verification of Fairisle ATM (Asynchronous Transfer Mode) switch [9] Modular means to verify the equivalence between submodules of the behavioral and RTL models, or submodules of RTL and synthesized gate level models. Although such ....

J. Lu and S. Tahar, "Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS," Proc. IEEE 8th Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, pp. 368-373. February 1998.

....timing behavior. From this verification, the author found no error in the fabricated implementation. However, several errors in the formal specifications were found, highlighting the fact that a correct specification could be just as hard to develop as an implementation. More recently, Lu et al. [22] used the VIS tool [4] to verify relevant liveness and safety properties (described in CTL) on various abstracted models of the Fairisle 4 4 switch fabric. In order to cope with the state explosion problem, the authors used several compositional reasoning techniques for properties division and had ....

....the verification of the complete fabric. Although Curzon [13] showed the effectiveness of HOL theorem proving for verifying an ATM switch, the use of HOL is interactive and requires much expertise to guide the verification process [19] In contrast, the ATM verification performed by Lu et al. [22] using VIS was automatic. While succeeding with model checking reduced models of the whole fabric and with equivalence checking of submodules of the design hierarchy, due to state space explosion, the VIS tool failed to complete the equivalence checking of even a very reduced model of the fabric. ....

[Article contains additional citation context not shown here]

J. Lu and S. Tahar, "Practical approaches to the automatic verification of an ATM switch fabric using VIS," in Proc. IEEE 8th Great Lakes Symp. VLSI (GLS-VLSI'98), Lafayette, LA, Feb. 1998, pp. 368--373.

....groups have also used the 4 by 4 fabric as a case study. Jakubiec and Coupet Grimal are using it in their work using the Coq proof system for hardware verification [17] Garcez [11] has also verified some properties of the 4 by 4 fabric using the HSIS model checking tool [2] More recently, Lu [21] used the VIS tool [3] to perform property checking on various abstracted models of the fabric. In addition, he conducted equivalence checking between behavioral and structural specifications of submodules of the fabric written in Verilog. He also re implemented the whole fabric using the Synopsys ....

Lu , J. and Tahar, S. 1998. Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS. In Proceedings of Great Lakes Symposium on VLSI, Lafayette, Louisiana, USA, 368--373.

....this step would be useful to verify if the logic synthesis is correct. As an alternative to equivalence checking, we attempted model checking of the switch fabric. Unlike MDG, model checking is the main verification approach in VIS. As for the MDG approach an environment state machine was needed [11]. To ease the model checking we compressed the 68 states into 7 states. Again we failed to verify the whole switch fabric due to the state space explosion. We succeeded in model checking a simplified fabric with its datapath and control path reduced from 8 bits to the minimum 1 bit and 4 bits, ....

....to be reduced to 4 bits and the datapath further to one bit to enable the model checking procedure to terminate. The control path could not be reduced below 4 bits as the data includes the header control information. For more details about the abstraction and reduction techniques adopted refer to [11]. We gave the behavioral specification of the fabric in two forms: an RTL description as a state machine of the whole fabric and a set of liveness and safety properties covering its essential behavior. In addition, as with HOL, behavioral specifications of submodules of the design hierarchy were ....

[Article contains additional citation context not shown here]

J. Lu and S. Tahar. Practical Approaches to the Automatic Verification of an ATM Switch Fabric using VIS. In Proc. IEEE Great Lakes Symp. on VLSI, 368--373, 1998.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC