Perry, T. S., "Intel's secret is out," IEEE Spectrum, Vol. 26, No. 4, April 1989. pp. 22-28,  Home/Search   Document Not in Database   Summary   Related Articles   Check

....that the break even point for the multithreaded processor occurs for a component density of between three and eight times that of the Stanford MIPS X implementation. The Stanford MIPS X processor uses about 150,000 transistors[9] The Intel 80860 processor uses more than one million transistors[18]. Thus, the break even component density is reasonable. 5.3. External Cache Effects Figure 7 shows the CPI of both processors vs. external cache size for various instruction cache configurations. The external cache does not affect the CPI as greatly as the instruction cache since it has a low ....

Perry, T. S., "Intel's secret is out," IEEE Spectrum, Vol. 26, No. 4, April 1989. pp. 22-28,

....while staticallyscheduled superscalar processors refer to instructions within a single fetch block. A VLIW operation is equivalent to a superscalar instruction since both control a single functional unit. Many statically scheduled machines have been announced either as superscalar processors [1, 17] or as VLIW processors [4] Unfortunately, all these machines encounter difficulties when scheduling across conditional branches even though software branch prediction can be as accurate as hardware branch prediction [13] Delay branch schedulers are able to perform some limited movement of ....

T.S. Perry, "Intel's Secret Is Out." IEEE Spectrum (April 1989), pp. 22-28.

....instruction fetch mechanism can grow excessively. In the early stages of the design of the i860, the instruction cache and amplifiers drew too much power. Tuning the design reduced the instruction cache energy budget to about . 5 watt, approximately one sixth of the 3 watts drawn by the entire chip [Per89]. 3 Energy and State Changes Global energy dissipation of a CMOS circuit over some period of time can be approximated based on the number of node state changes that occur during that time and switching energy at each node. Let e i be the energy dissipated to effect a state change at node i, and ....

Tekla S. Perry. Intel's secret is out. IEEE Spectrum, 26(4):22--28, April 1989.

....operate frequently, power to operate the instruction fetch mechanism can be a problem. In the design of the i860, the instruction cache and amplifiers were initially inefficient; tuning the design reduced instruction cache power to about . 5 watts, one sixth of the energy budget for the entire chip [61]. In the remainder of this chapter, we examine techniques for reducing instruction fetch power dissipation. We relate power dissipation to instruction traffic, and estimate power dissipation differences between the D16 and DLXe instruction sets. We explore the effects of cache organization, and ....

Tekla S. Perry. Intel's secret is out. IEEE Spectrum, 26(4):22--28, April 1989.

.... evidence that this prediction is well within reason, the following table demonstrates the rapid growth in the transistor count of CMOS processors since Myers et al. made their prediction: year processor name number of transistors reference 1985 Intel i80386 275,000 [86] 1989 Intel i860 1,000,000 [73, 93] 1991 Intel i860 XP 2,500,000 [61] Sun SuperSPARC 3,100,000 As shown by the transistor counts for 1989 and 1991, this growth rate is expected to increase to 1.5 as memory, which is denser than processor logic, is integrated with the processor. Based on these growth trends, producing a ten million ....

Tekla S. Perry. Intel's secret is out. IEEE Spectrum, 26(4):22--28, April 1989.

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