K. Kissell. MIPS16: High-Density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....However, in the literature there also exist several attempts and approaches to both compact the code and to utilize instructions of variable length in RISC machines. The most widely known approaches to reduce the length of RISC style instructions are the ARM Thumb and the MIPS16 instruction sets [10, 16]. Both Thumb and MIPS16 are pure subsets of the normal ARM and MIPS instruction sets using 16 bit instead of 32 bit instructions. This is possible through restrictions in the usage of the register set and of addressing modes as compared to the original 32 bit instruction sets. The usage of mixed ....

K. D. Kissell. MIPS16: High-density MIPS for the Embedded Market, in Proceedings of Real Time Systems '97 (RTS97), 1997.

....plenty of 32 bit RISC architectures, most of them are designed around a 32 bit instruction word and suffer from poor code density for embedded applications. In order to address this code size problem, ADC s 32 bit EISC processors use an approach similar to those of ARM s Thumb [8] and MIP s MIPS16 [9], i.e. facilitating a 32 bit data processing with an efficient 16 bit instruction coding. This approach provides better performance than a 16 bit processing scheme with better code density than a 32 bit instruction coding [8, 9] The chip is in production and is currently used in applications ....

....use an approach similar to those of ARM s Thumb [8] and MIP s MIPS16 [9] i.e. facilitating a 32 bit data processing with an efficient 16 bit instruction coding. This approach provides better performance than a 16 bit processing scheme with better code density than a 32 bit instruction coding [8, 9]. The chip is in production and is currently used in applications such as Karaoke systems, game machines, video editors, and set top boxes. This paper is organized as follows. Related work in the field of exceptions and embedded processors is discussed in the following section. Section 3 ....

K. D. Kissell, MIPS16: High-density MIPS for the Embedded Market, Proceedings of Real Time Systems, 1997.

....to access only 8 general purpose registers (out of a possible 16 in normal mode) and can encode only small immediate val ues. Experimental results show a compression factor of 30 with 10 15 decrease in performance using the Thumb IS. The MIPS ISA features a 16 bit extension called MIPS16 IS[10]. MIPS16 IS contains an extend op code which extends the values of immediate operands that were otherwise not representable because of bitwidth constraints. There are no explicit mode change instructions to switch between the 32 bit and 16 bit IS. Rather, code alignment dictates the mode of ....

K. Kissell. MIPS16: High-density MIPS for the embed- ded market. Technical report, Silicon Graphics MIPS Group, 1997.

....to access only 8 general purpose registers (out of a possible 16 in normal mode) and can encode only small immediate values. Experimental results show a compression factor of 30 with 10 15 decrease in performance using the Thumb IS. The MIPS ISA features a 16 bit extension called MIPS16 IS[10]. MIPS16 IS contains an extend opcode which extends the values of immediate operands that were otherwise not representable because of bitwidth constraints. There are no explicit mode change instructions to switch between the 32 bit and 16 bit IS. Rather, code alignment dictates the mode of ....

K. Kissell. MIPS16: High-density MIPS for the embedded market. Technical report, Silicon Graphics MIPS Group, 1997.

....bytecode, the average overall compression factor is 60 . 1 Introduction 1.1 Motivation Embedded systems are resource constrained devices requiring careful attention to memory usage and power consumption. To serve these goals, several researchers are taking the approach of reducing program size [6, 26, 2, 13, 11, 12]. Recently, IBM has developed CodePack [11, 12] to compress programs for the PowerPC processor for the embedded market. Others have developed dual processors that switch between compressed and uncompressed modes of decoding [13, 2] To tackle such systems in Java, Sun has taken the approach of ....

....are taking the approach of reducing program size [6, 26, 2, 13, 11, 12] Recently, IBM has developed CodePack [11, 12] to compress programs for the PowerPC processor for the embedded market. Others have developed dual processors that switch between compressed and uncompressed modes of decoding [13, 2]. To tackle such systems in Java, Sun has taken the approach of de ning a small virtual machine, the KVM [26] The KVM uses on the order of 128K, including libraries. The virtual machine itself is 40K 80K depending on the compiler and the target platform used. Programs (Sample) ....

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K. Kissell. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

....instruction sets provide denser code without the complexity of compression and decompression, but are ill suited for pipelined or superscalar execution. 2.1 Compression of RISC ISAs Most of the previous work in code compression has focused on RISC architectures. The ARM Thumb [25] and MIPS16 [20] instruction sets provide alternate 16 bit versions of the base fixed length RISC ISA (ARM and MIPS respectively) to improve code density. Decompression is a straightforward mapping from the short instruction format to the wider instruction format in the decode stage of the pipeline. Both ISAs ....

Kevin D. Kissell. MIPS16: High-density MIPS for the embedded market. In Proceedings RTS97, 1997.

....our system does not incur the memory cost of a byte code interpreter. There has been a significant amount of work on architectural extensions for the execution of compressed code: examples include Thumb for ARM processors [3] CodePack for PowerPC processors [15] and MIPS16, for MIPS processors [16]. Special hardware support is used to expand each compressed instruction to its executable form prior to execution. While such an approach has the advantage of not incurring the space overheads for control stubs and time overheads for software decompression, the requirement for special hardware ....

K. D. Kissell. MIPS16: High-density MIPS for the Embedded Market. Proc. Real Time Systems '97 (RTS97), 1997.

....compress 32 bit long instructions to a smaller but fixed bit size of compressed instructions. Other research has focused on architectural issues. Industrial approaches to modify the processor architecture to accomplish execution of compressed code have been conducted for the MIPS architecture [11] and for the ARM Thumb architecture [12] Both of these approaches modify the decoding unit of the particular processor. Wolfe et al. 3] focused on a pre cache architecture i.e. a stand alone decompression unit that is located between main memory and cache. Other approaches do not investigate ....

K.D. Kissell, MIPS16: High Density MIPS for the Embedded Market, Silicon Graphics Group, 1997.

....of the total memory footprint of the data structures required by other analyses in Squeeze. 8. RELATED WORK There is a considerable body of work on code compression, but much of this focuses on compressing executable les as much as possible in order to reduce storage or transmission costs [10, 11, 12, 13, 16, 17, 19]. These approaches generally produce compressed representables that are smaller than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [10, 11, 12, 13] which can be problematic for limited memory ....

.... than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [10, 11, 12, 13] which can be problematic for limited memory devices or require special hardware support for executing the compressed code directly [16, 17]. By contrast, programs compacted using our techniques can be executed directly without any decompression or special hardware support. Most of the previous work on code compaction to yield smaller executables treats an executable program as a simple linear sequence of instructions [3, 6, 14] ....

K. D. Kissell. MIPS16: High-density MIPS for the embedded market. In Proc. Real Time Systems '97 (RTS97), 1997.

....the current instruction set used to decode instructions. This allows a program to have the advantages of wide, expressive instructions for high performance and short instructions for code density. ARM and MIPS are examples of such dual mode instruction sets. Thumb [ARM95, Turley95] and MIPS 16 [Kissell97] are defined as the 16 bit instruction set subsets of the ARM and MIPS III architectures. A wide range of applications were analyzed to determine the composition of the subsets. The instructions included in the subsets are either frequently used, do not require a full 32 bits, or are important to ....

....are either frequently used, do not require a full 32 bits, or are important to the compiler for generating small object code. The original 32 bit wide instructions have been re encoded to be 16 bits wide. Thumb and MIPS 14 16 are reported to achieve code reductions of 30 and 40 , respectively [ARM95, Kissell97]. Thumb and MIPS 16 instructions have a one to one correspondence to instructions in the base architectures. In each case, a 16 bit instruction is fetched from the instruction memory, decoded to the equivalent 32 bit wide instruction, and passed to the processor core for execution. The 16 bit ....

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K. Kissell, MIPS16: High-density MIPS for the Embedded Market, Technical report, Silicon Graphics MIPS Group, 1997.

....for the relative size of 1) code in the compacted binaries 2) data in the compacted binaries 3) code removed when applying code compaction only 4) additional code removed due to combined analysis and 5) data removed from the program. Each program is annotated with its full size in MB. sion costs [8, 9, 10, 11, 14, 15, 17]. These approaches generally produce compressed representables that are smaller than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [8, 9, 10, 11] which can be problematic for limited memory ....

.... than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [8, 9, 10, 11] which can be problematic for limited memory devices or require special hardware support for executing the compressed code directly [14, 15]. By contrast, programs compacted using our techniques can be executed directly without any decompression or special hardware support. Most of the previous work on code compaction to yield smaller executables treats an executable program as a simple linear sequence of instructions [3, 6, 12] ....

K. D. Kissell. Mips16: High-density mips for the embedded market. In Proc. Real Time Systems '97 (RTS97), 1997.

....the dynamically linked programs consist for a large part of a dynamic string and symbol table. 6. RELATED WORK There is a considerable body of work on code compression, but much of this focuses on compressing executable files as much as possible in order to reduce storage or transmission costs [8, 10, 11, 12, 14, 15, 17]. These approaches generally produce compressed representables that are smaller than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [8, 10, 11, 12] which can be problematic for limited memory ....

.... those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [8, 10, 11, 12] which can be problematic for limited memory devices or require special hardware support for executing the compressed code directly [14, 15]. By contrast, programs compacted using our techniques can be executed directly without any decompression or special hardware support. Most of the previous work on code compaction to yield smaller executables treats an executable program as a simple linear sequence of instructions [3, 5, 13] ....

K. D. Kissell. Mips16: High-density mips for the embedded market. In Proc. Real Time Systems '97 (RTS97), 1997.

....level which brings more opportunity for compaction. They obtain an average 78 factor of compression. Hoogerbrugge et al. 10] have very good results in producing compact code and in spirit it is one of the closest work to ours. It is similar to the ideas found in the Thumb and MIPS16 processors [21, 13] where only a part of the program is compressed. It gives a faster execution by compressing only the less used parts. A tailored VM is automatically generated given a C program. They obtain a 70 factor of compression when comparing the native codes. Closer to Scheme, Scheme 48[11] is a compact ....

K. Kissell. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

....level which brings more opportunity for compaction. They obtain an average 78 factor of compression. Hoogerbrugge et al. 11] have very good results in producing compact code and in spirit it is one of the closest work to ours. It is similar to the ideas found in the Thumb and MIPS16 processors [22, 14] where only a part of the program is compressed. It gives a faster execution by compressing only the less used parts. A tailored VM is automatically generated given a C program. They obtain a 70 factor of compression when comparing the native codes. Closer to Scheme, Scheme 48[12] is a compact ....

K. Kissell. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

....to the code and data compaction, but also to the removal of unnecessary stack spills by Squeeze. 8. RELATED WORK There is a considerable body of work on code compression, but much of this focuses on compressing executable les as much as possible in order to reduce storage or transmission costs [5, 6, 7, 8, 11, 12]. These approaches generally produce compressed representables that are smaller than those obtained using our approach, but have the drawback that they must either be decompressed to their original size before they can be executed [5, 6, 7, 8] which can be problematic for limited memory devices or ....

....Number of instructions and binary program size in bytes for the benchmarks generated by the GNU compilers (base) after code compaction and after combined code and data compaction. The ratio s given are all compared to the base binaries. hardware support for executing the compressed code directly [11, 12]. By contrast, programs compacted using our techniques can be executed directly without any decompression or special hardware support. Most of the previous work on code compaction to yield smaller executables treats an executable program as a simple linear sequence of instructions [1, 3, 9, 18] ....

K. D. Kissell. Mips16: High-density mips for the embedded market. In Proc. Real Time Systems '97 (RTS97), 1997.

....less expressive than 32 bit instructions, which causes the number of instructions executed in the 16 bit instruction programs to increase. They report that the performance penalty for executing more instructions was often offset by the increased fetch efficiency. Thumb [ARM95, MPR95] and MIPS16 [Kissell97] are two examples. Programs compiled for Thumb achieve 30 smaller code in comparison to the standard ARM instruction set, but run 15 20 slower on systems with ideal instruction memories (32 bit buses and no wait states) ARM95] Code written for 32 bit MIPS III is typically reduced 40 in size ....

.... compiled for Thumb achieve 30 smaller code in comparison to the standard ARM instruction set, but run 15 20 slower on systems with ideal instruction memories (32 bit buses and no wait states) ARM95] Code written for 32 bit MIPS III is typically reduced 40 in size when compiled for MIPS16 [Kissell97]. 2.2 CCRP The Compressed Code RISC Processor (CCRP) described in [Wolfe92, Kozuch94] has an instruction cache that is modified to run compressed programs. At compile time the cache line bytes are Huffman encoded. At run time cache lines are fetched from main memory, decompressed, and put in the ....

K. Kissell, MIPS16: High-density MIPS for the Embedded Market, Silicon Graphics MIPS Group, 1997.

....have a small critical part where most of the execution time is spent, several recently introduced processors have been designed with two execution modes: one for high code density and one for high execution speed. Examples of these dual mode processors are the ARM Thumb [2] and the MIPS16 [3]. If only a small part of an application is performance critical, a dual mode processor can achieve the code size of a processor designed for high code density, and the performance of a processor designed for high execution speed. An alternative for dual mode processors is a high performance, low ....

K. Kissell, MIPS16: High-density MIPS for the Embedded Market, Silicon Graphics MIPS Group, 1997.

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K. Kissell. MIPS16: High-Density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

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Kissell, K. MIPS16: High-density MIPS for the Embedded Market. In Proc. Conf. Real Time Systems (RTS'97) (1997).

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Kissell, K. MIPS16: High-density MIPS for the embedded market. In Proc. Conf. Real Time Systems (RTS'97) (1997).

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K. Kissell. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

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K. Kissell. MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

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K. D. Kissell. MIPS16: High-density MIPS for the embedded market. In Proc. of Real Time Systems '97 (RTS97), 1997.

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K. Kissell. MIPS16: High-Density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

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Kissell, MIPS16: High-density MIPS for the Embedded Market. Silicon Graphics MIPS Group, 1997.

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