S. J. Eggers and R. H. Katz. "Evaluating the Performance of Four Cache Coherence Protocols". In the 16th International Symposium on Computer Architecture, pp. 2-15, May 1989. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
The "T" Enhancement of Cache Coherent Protocols - Avi Mendelson And (Correct)
.... multicache system has to take into consideration two basic phenomena which are different from the design of a regular cache: 1) when large cache lines are used, it can cause a false sharing and so reduce the advantage of using large cache lines, and (2) when large caches are used, it was reported [3,4] that the number of coherence related activities increases as well. This phenomenon was reported without any satisfying explanations, since the amount of coherent related activities should not be increased when larger caches are used. A possible explanation can be found by looking at the ....
S. J. Eggers and R. H. Katz. "Evaluating the Performance of Four Cache Coherence Protocols". In the 16th International Symposium on Computer Architecture, pp. 2-15, May 1989.
The Effect of "Seance Communication" on Multiprocessing Systems - Avi Mendelson And (Correct)
....modification of shared, or potentially shared data, either by invalidating all the corresponding copies of the data present in other caches, or by updating them. The performance of multiprocessors depends on the sharing patterns of the application being run. Various works, such as [Egge88] and [Egge89], have widely studied and analyzed the impact of the sharing patterns on different cache coherency protocols. Their results indicate that write update protocols can outperform write invalidate protocols when the application is characterized with finegrain sharing, but may perform relatively ....
....patterns that might have a considerable impact on the system performance, other design parameters can affect the system performance: 1) Large cache lines can cause false sharing and so reduce their benefits. False sharing may cause an overhead in both write invalidate and write update protocols ([Egge89]) 2) When large caches are used, it was reported by Eggers and Katz ( Egge88] and [Egge89] that the number of coherency related activities increases as well. This phenomenon was not explained, maybe because the relationship between the amount of coherency related activities and the cache size ....
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S. J. Eggers and R. H. Katz. Evaluating the Performance of Four Cache Coherence Protocols. In the 16th Int'l Symp. on Computer Architecture, pp. 2 - 15, 1989.
Smart: An Advanced Shared-Memory Simulator - Towards a.. - Freddy Gabbay (Correct)
....we can either gather statistics on the distribution of cache lines and or present them so that the user can trace the content of the cache along the execution. 4.2. Sharing patterns in shared memory architectures. Sharing patterns can dominate the performance of shared memory systems ( Egge88] [Egge89] and [Mend96a] In addition various cache coherency protocols were proposed to better utilize these sharing patterns. Most previous works on the performance of cache coherency protocols did not take into account the impact of system activities on the sharing patterns. Smart can visualize and ....
S. J. Eggers and R. H. Katz. Evaluating the Performance of Four Cache Coherence Protocols. In the 16 th International Symposium on Computer Architecture, pp. 2 - 15, 1989.
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