R. Jain, A. Mujumdar, A. Sharma, and H. Wang. Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. In Proc. Design Automation Conf., pages 686--689, June 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....that was chosen for the scheduling task of the HLS method. In the work reported here, force directed scheduling has been replaced by list scheduling, which is known for its sim plicity and low computational requirements (see e.g. 5] while still producing results of comparable or better quality [10, 12]. List scheduling uses a list of ready operations, operations of which all predecessors have already been scheduled, and a priority function, a function that decides which operation in the list should be scheduled next. This operation is scheduled at the earliest control step at which an FU of ....

R. Jain, A. Mujumdar, A. Sharma, and H. Wang. Empirical evaluation of some highlevel synthesis scheduling heuristics. In 28th Design Automation Conference, pages 686-689, 1991.

.... On error indication for totally selfchecking systems, IEEE Trans. Comput. vol. C 36, pp. 1389 1391, Nov. 1987. 9] R. A. Parekhji, G. Venkatesh, and S. D. Sherlekar, A methodology for designing optimal self checking sequential circuits, in Proc. IEEE Int. Test Conf. 1991, pp. 283 291. [10] I. Jansch and B. Courtois, Design of SCD checkers based on analytical hypotheses, in Proc. 10th Eur. Solid State Circuits Conf. 1984, pp. 109 112. 11] J. Shen, W. Maly, and F. Ferguson, Inductive fault analysis of MOS integrated circuits, IEEE Design Test Comput. pp. 26 33, Dec. 1985. ....

.... In this note, we show that the phase assignment problem is exactly equivalent to the resource constrained operation scheduling problem in high level synthesis (HLS) Because the problem has been extensively studied in the HLS community, we propose adopting the static list scheduling method [10] for the phase assignment problem. The rest of the note is organized as followed. In Section II, we describe a typical hardware emulator architecture. The concept of virtual wire is described in Section III. Section IV defines the phase assignment problem, and proposes the assignment approach. ....

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R. Jain, A. Mujumdar, A. Sharma, and H. Wang, "Empirical evaluation of some high-level synthesis scheduling heuristics," in Proc. 28nd ACM/IEEE Design Automation Conf., June 1991, pp. 210--215.

....fu, would minimize the expected number of cycles. The above problem has been proven NP complete, even for conditional and loop free behavioral descriptions [26] We, therefore, use the following heuristic, whose guiding principle has been successfully employed by several scheduling algorithms [27]. The heuristic is based on the following premise: operations in the CDFG which feed primary outputs through long paths are more critical than operations which feed primary outputs through short paths and, therefore, need to be scheduled earlier. The rationale behind this heuristic is that ....

R. Jain, A. Majumdar, A. Sharma, and H. Wang, "Empirical evaluation of some high-level synthesis scheduling heuristics," in Proc. Design Automation Conf., pp. 686--689, June 1991.

....would minimize the expected number of cycles. The above problem has been proven to be NP complete, even for conditional and loop free behavioral descriptions [8] We, therefore, use the following heuristic, whose guiding principle has been successfully employed by several scheduling algorithms [9]. The heuristic is based on the following premise: operations in the CDFG which feed primary outputs through long paths are more critical than operations which feed primary outputs through short paths and, therefore, need to be scheduled earlier. The rationale behind this heuristic is that ....

R. Jain, A. Majumdar, A. Sharma, and H. Wang, "Empirical evaluation of some high-level synthesis scheduling heuristics," in Proc. Design Automation Conf., pp. 686--689, June 1991.

.... used by many systems under different priority functions [32, 57, 61] Some typical priority functions are as late as possible time, the number of descendants, and the difference between as soon as possible and as late as possible times (mobility) 61] Several scheduling algorithms are compared in [37]. Force directed scheduling [67] uses the probability distribution of operations being executed in each time step to balance the amount of hardware required. Forcedirected scheduling has been shown to have very good performance. However, it is computationally more expensive than most list ....

Jain, R., Mujumdar, A., Sharma, A., and Wang, H. Empirical evaluation of some high-level synthesis scheduling heuristics. In Proceedings of the ACM/IEEE Design Automation Conference (1991), pp. 210--215.

....that was chosen for the scheduling task of the HLS method. In the work reported here, force directed scheduling has been replaced by list scheduling, which is known for its simplicity and low computational requirements (see e.g. 5] while still producing results of comparable or better quality [10, 12]. List scheduling uses a list of ready operations, operations of which all predecessors have already been scheduled, and a priority function, a function that decides which operation in the list should be scheduled next. This operation is scheduled at the earliest control step at which an FU of the ....

R. Jain, A. Mujumdar, A. Sharma, and H. Wang. Empirical evaluation of some highlevel synthesis scheduling heuristics. In 28th Design Automation Conference, pages 686--689, 1991.

....Over the years, however, DSP scheduling in its classical form lost some of its importance due to a variety of reasons. Extensive empirical studies have indicated that different competing scheduling techniques have relatively small impact on the key design metrics of the final implementation [6]. Recently developed estimation techniques have also indicated that there is little room for further improvement of scheduling algorithms [2] 21] More importantly, there has been strong evidence that other behavioral synthesis tasks, in particular transformations, can have a significantly higher ....

R. Jain et al., "Empirical Evaluation of Some High-level Synthesis Scheduling Heuristics", Design Automation Conference, pp. 686-689, 1991.

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R. Jain, A. Mujumdar, A. Sharma, and H. Wang. Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. In Proc. Design Automation Conf., pages 686--689, June 1991.

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R. Jain, A. Mujumdar, A. Sharma, and H. Wang. Empirical evaluation of some high-level synthesis scheduling heuristics. In DAC '91, pages 210--215, 1991.

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R. Jain, A. Majumdar, A. Sharma, and H. Wang, "Empirical Evaluation of Some HighLevel Synthesis Scheduling Heuristics," in Proceedings of the 28th Design Automation Conference, 1991, pp. 210--215.

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Jain, R., Mujumdar, A., Sharma, A. and Wang, H. (1991) Empirical evaluation of some high-level synthesis scheduling heuristics. In Proc. 28th ACM/IEEE Design Automation Conf., pp. 686--689.

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