S. Naffziger. A sub-nanosecond 0.5mm 64b adder design. In ISSCC Dig. Tech. Papers, pages 362--363, Feb. 1996. Home/Search Document Not in Database Summary Related Articles Check |
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Reduced Latency IEEE Floating-Point Standard Adder.. - Beaumont-Smith.. (Correct)
.... distance can be done by a leading zero anticipator to provide the normalisation shift to within one bit, in parallel with the significand addition [8] ffl a fast integer adder is crucial to the design of FP adders for calculating the result significand and sets the minimum cycle time [14]. Further improvements in speed can be made by splitting the algorithm into two parallel data paths based on the exponent difference [5, 10, 3, 16, 15] namely near (jE a Gamma E b j 1) and far (jE a Gamma E b j 1) computations, by noting that the alignment and normalisation phases are ....
S. Naffziger. A sub-nanosecond 0.5mm 64b adder design. In ISSCC Dig. Tech. Papers, pages 362--363, Feb. 1996.
VLSI Datapath Choices: Cell-Based Versus Full-Custom - Chang (1998) (4 citations) (Correct)
....dynamic circuit techniques. 3.6 Survey of Adders The 64 bit adder subtractor [44] used in the MAP chip is a hybrid carry lookahead carryselect design implemented in a static CMOS circuit style and includes N only pass gates. Many adder designs have been reported in the literature. Four [58] 28] [70] [77] are summarized in Tables 3.14 and 3.15 for comparison to the MAP ADDSUB. In addition, an analytic model [21] was used to estimate both the area and performance of the ADDSUB. The model estimates the area of a 64 bit carry select adder to be 1.3M 2 and the t PD to be equal to 400 C . For ....
Naffziger, S. A Sub-Nanosecond 0.5Żm 64b Adder Design. http://www.hp.com/computing/framed/technology/micropro/.
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