L. Gwennap. TFP designed for tremendous floating point. Microprocessor Report, pages 9--13, August 1993. Home/Search Document Not in Database Summary Related Articles Check |
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Vector Microprocessors - Asanovic (1998) (17 citations) (Correct)
....8400 have a 16 byte L3 cache bus that cycles at a 75MHz clock rate [FFG 95] The 75 MHz R8000 processors in the Power Challenge have a 16 byte L2 cache bus cycling at 75 MHz. The R8000 is split into two chips with the separate floating point unit chip connected directly to the L2 cache [Gwe93] All the floating point loads and stores used in the STREAM benchmark do not access the L1 cache on the integer unit chip. The 167MHz UltraSPARC processors in the Sun UE 6000 system have a 16 byte L2 cache bus cycling at 167MHz. The fourth column gives the maximum aggregate application memory ....
....and data page faults. 4.6.1 Handling Vector Arithmetic Traps Without some form of revocable register renaming, a vector machine will not be able to provide precise vector arithmetic traps without a large performance loss. Some scalar systems make precise traps a user selectable mode [WD93, Gwe93] In this mode, further instruction issue must be delayed until all ongoing operations are known not to require a trap. This scheme can also be used in a vector machine. Whereas a scalar machine must delay after every operation, a vector machine is only delayed once per vector, but this delay can ....
L. Gwennap. TFP designed for tremendous floating point. Microprocessor Report, pages 9--13, August 1993.
VLSI Datapath Choices: Cell-Based Versus Full-Custom - Chang (1998) (4 citations) (Correct)
....Several vendors are predicting the realization of 100 Million and 1 Billion transistor logic chips in the near future. How best to employ these transistors 1 The data for this graph comes from a wide range of sources [2] 4] 8] 11] 13] 16] 18] 19] 29] 30] 33] 32] 39] 41] 42] 45] [49] [46] 47] 52] 51] 55] 60] 73] 74] 76] 75] Processor Trends 1979 1997 0.00E 00 1.00E 09 2.00E 09 3.00E 09 4.00E 09 5.00E 09 6.00E 09 7.00E 09 8.00E 09 9.00E 09 1.00E 10 MOT 68000 Hitachi Matsushita i486DX2 MIPS 4600 MIPS 4400SC HP 7200 TI 320C80 DEC 21064a MIPS R4400 IBM PP620 Sun Ultra ....
Gwennap, L. TFP Designed for Tremendous Floating Point. Microprocessor Report (August 23 1993), 9--13.
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