D.Auvergne, N.Azemard, V.Bonzom, D.Deschacht, M.Robert, "Formal sizing rules of CMOS circuits", EDAC 91, Amsterdam, 1991, pp. 96-100. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A New Layout Style For High-Performance Circuits - Moraes (Correct)
....to the layout synthesis. After the logical synthesis, the parasitic elements (routing, diffusion and polisilicon) will be evaluated by the layout synthesis tool, returning the expected delay [MOR95] If the delay condition is not attempted, the following approaches can be used: transistor sizing [AUV91], template selection [FAN95] for the standard cells approach) buffer insertion [AZE92] or execute a second logical synthesis, changing some cost functions to improve performance. The delay prediction reduces the design time, because it s not necessary to do the layout synthesis, the layout ....
....region, for different circuits and technologies (from 2.0m to 0.7 m) begins when the transistor width is around 8 to 10 times the minimum size. This is the initial solution for the transistor widths. After the layout synthesis, using the regular solution, the transistors sizes are calculated [AUV91], taking into account the routing capacitances. The sizing solution allows a better symmetry between rise and fall times, and a total active area reduction. Conclusion In this paper, a new layout style was presented. It minimizes the diffusion capacitances and the polisilicon length by using 3 ....
D.Auvergne, N.Azemard, V.Bonzom, D.Deschacht, M.Robert, "Formal sizing rules of CMOS circuits", EDAC 91, Amsterdam, 1991, pp. 96-100.
VLSI Datapath Choices: Cell-Based Versus Full-Custom - Chang (1998) (4 citations) (Correct)
....cell placement; parameter studies on cell size and performance sensitivity; case studies implementation examples; and effort studies. Both optimal and heuristic solutions to the topics of compaction, configuration, sizing, and geometry in layout synthesis have been investigated extensively [1] [5] [10] 14] 56] 62] Researchers have also extensively posited, implemented and studied automated optimization of cell placement and floorplanning [3] 15] 20] 31] 38] 64] The sensitivities of circuits and physical design to a wide range of parameters including process feature size, number ....
Auvergne, D., Azemard, N., Bonzom, V., Deschacht, D., and Robert, M. Formal Sizing Rules of CMOS Circuits. In Proceedings of ICCD (1991), IEEE, pp. 96--100.
Design and Selection of Buffers for Minimum Power-Delay.. - Turgis, Azemard, Auvergne (1996) Self-citation (Auvergne Azemard) (Correct)
....20 30 energy saving in designing multistage variable tapered buffers from multivariable Kuhn Tucker optimization. CAD tools have been proposed to size gates [13,14,15] moreover they use numerical programming techniques which are far to be intuitive for designers. An exception is offered in [16] where a local optimization has been used to define explicit sizing equations for equal rise and fall times on individual gates, resulting in a variable taper implementation with smaller area than that obtained with global methods. The last published work to date addresses the problem of buffer ....
D.Auvergne, N.Azemard, V.Bonzom, D.Deschacht, M.Robert "Formal sizing rules of CMOS circuits", EDAC, European Design Automation Conference, pp 96-100, Amsterdam, 25-28 February 1991.
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