K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," in Proc. IEEE GLOBECOM'89, Dallas, TX, Nov. 1989, pp. 1159--1165.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....ATM switch. It was then modified to cope with the multicast capability [8] in which we showed that a switch that is designed to meet the performance requirement for unicast calls will also satisfy multicast calls performance. Both architectures employed the generalized Knockout concept [9] with output buffers. However, both switch fabrics are a lossy system, where cells may be discarded when the number of routing links are less than the number of incoming cells destined for the same output port (or output group) Here, we propose a new architecture eliminating the probability that ....

K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: design principles and applications," IEEE Trans. Commun., vol. COM-40, no. 2, pp. 423-430, Feb. 1992.

....switch. Hence a path allocation algorithm must be employed to select among the available paths. A distinction is made between two time scales over which path allocations may be performed: Call level; Cell level. Cell level path allocation has been proposed in the Growable packet switch [10] and in our channel grouped switch [11] Most other proposals for three stage ATM switches have featured call level path allocation. 4.2 .Call level path allocation The condition already developed for circuit switching can be applied to the call level case. The bit rate of a call can vary ....

K.Y. Eng et al., "A growable packet (ATM) switch architecture: design principles and applications"; Globecom '89 Conference Record, pp. 1159-1165 , 1989.

....allowing the switch fabric to be distributed across multiple boards or cabinets. An obvious method of implementing a large switch, given these constraints, is to design the switch with three stages, where each stage consists of smaller switch modules. Many authors have proposed such switches [5 9]. This approach typically introduces a new problem (not present in a single stage switch) whereby multiple paths from source to destination become available. Thus, even if the individual switch modules possess the self routing feature, this feature is not retained by the overall switch. Some ....

....input and intermediate stage modules, and S 2 links in the channel group connecting intermediate and output stage modules. The use of channel grouping allows additional flexibility when dimensioning the three stage switch. Cell level path allocation has been proposed by a number of authors [5 7]. The algorithm described here requires fewer iterations than that in [6] does not require input buffering (which degrades the throughput) unlike [7] and is fairer than that presented in [5] in addition to readily supporting intermediate channel grouping. The path allocation algorithm and the ....

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K.Y. Eng, M.J. Karol and Y.-S. Yeh, "A growable packet (ATM) switch architecture: design principles and applications," IEEE Trans. Commun., vol. 40, no. 2, pp. 423-430, Feb. 1992.

....throughput [2] A multi stage switch architecture is a feasible and cost e#ective way to make such a system. A threestage Clos architecture is the best architecture in terms of switch scalability because it can be expanded easily using the same switching block, but it has two basic problems [3] [5]. One is that if connection based routing (in which all cells belonging to the same virtual channel (VC) take the same path through the multistage switch) is used, this architecture needs resource management in the switches in the intermediate stage to avoid overloading conditon caused by multiple ....

K.Y. Eng, M.J. Karol, and Y.S. Yeh, "A growable packet (ATM) switch architecture: Design and application," IEEE Trans. Commun., pp.423--230, 1992.

....an application where the communication pattern is regular and the probability of contention is low. A number of other groups [124] 125] 126] 158] 127] 128] 129] have investigated optoelectronic switch designs that employ similar technology but are based on the Growable Packet Switch architecture [130][131] and would be more suitable for building large telecommunications switches. 41 3.3.2 Logical implementation This section briefly describes the structure of the digital electronics used to implement the functionality just described. More details about the digital electronics that implement ....

ENG, K.Y., KAROL, M.J., YEH, Y.-S.: `A growable packet (ATM) switch architecture: design principles and applications', IEEE Trans. Commun., February 1992, 40 (2), pp. 423-430

....ATM switch. It was then modified to cope with the multicast capability [11] in which we showed 2 that a switch that is designed to meet the performance requirement for unicast calls will also satisfy multicast calls performance. Both architectures employed the generalized Knockout concept [12] with output buffers. However, both switch fabrics are a lossy system, where cells may be discarded when the number of routing links are less than the number of incoming cells destined for the same output port (or output group) Here, we propose a new architecture eliminating the possibility of ....

K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: design principles and applications," IEEE Trans. Commun., vol. COM-40, no. 2, pp. 423-430, Feb. 1992.

....2 Remark 2.1 For ff 1 2 , Appendix B gives an example demonstrating that for n and S sufficiently large, some algorithms in BATCH MAXIMUM (and hence some algorithms in BATCH MAXIMAL ) do not have any of the properties P1 P3. The distributed routing algorithm for a packet switch described in [18] provides the inspiration for a class of algorithms introduced here called PARALLEL MAXIMAL, which is similar to the class BATCH MAXIMAL. For a given batch, consider an empty scheduling grid with n rows (representing the destinations) and 2ffS Gamma 1 columns (representing the departure slots ....

....packet, by the same reason used for BATCH MAXIMAL. Any strategy may be used by a source. If the sources proceed synchronously through n scheduling stages, and source i tries to schedule all of its packets destined for j during stage (i j) mod n, the algorithm is roughly equivalent to that of [18]. This strategy is attractive because multiple sources are not simultaneously considering the same destination during a given slot. Other strategies may include randomization, although the lowest average access delay is likely to be obtained by searching through the columns in order of increasing ....

K. Eng, M. Karol, and Y. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," IEEE Transactions on Communications, vol. 40, pp. 423--430, Feb. 1992.

....or even Terabits per second are a reality. At these rates, processing inside the network must be minimized. For example, at 2.4Gb s transmission rates, a processor has 177ns to switch an ATM cell. During this period, a 100MIPS processor can execute only 17 instructions. Recent HSN architectures [2, 8, 11, 12, 14, 18, 21, 22, 24, 30, 31, 32, 33, 34, 35, 36, 38] have directly addressed these issues by standing to a new design paradigm: relieve intelligence from the network, relaying functionality to its periphery. Network layer functions [29] such as routing and congestion control are shifted to the Media Access sublayer (MAC) being performed at the ....

Eng, K.Y., Karol, M.J., and Yeh, Y.S., "A growable packet (ATM) switch architecture: design principles and applications," in Proceedings of GLOBECOM, IEEE, Dallas, Texas, USA, November 1989, pp. 1159-1164.

....packet loss rate with finite buffer size. The paper is then concluded in section 4. 2. Maximum Throughput Consider a non blocking switch fabric with input output buffers as described in Fig.1, which is the most popular type of electronic packet switching architectures currently under development [5 9]. One advantage of this switch type is that no packet is queued within the switch fabric, which makes the control and management of the switch relatively simple. The switch inter connects N input links and N output links. Each link is logically partitioned into time slots of duration equal to one ....

K.Y.Eng, M.J. Karol and Y.S.Yeh, "A Growable Packet (ATM) Switch Architecture: Design Principles and Applications," Proc. of Globecom'89, Dec. 1989, pp. 32.2.1-7.

....(OSQ) 1] 2] 3] Of all queuing configurations, the IQ structure requires the least memory bandwidth for buffering ATM cells. Each queue module of an IQ switch only buffers cells at the arrival rate of a single port, rather than at a multiple of the arrival rate as with other structures [4] [5] [6] 7] 8] In addition, it has been found through simulation that with the same buffer size, an IQ switch has more tolerance for bursty traffic [9] Moreover, for multicast traffic, a burst of n cells that are to be delivered to m output ports only needs n cell buffers for the This research ....

K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A Growable Packet (ATM) Switch Architecture: Design Principle and Applications," IEEE Transactions on Communications, vol. 40, pp. 423--430, Feb. 1992.

....for each of the n outputs. These techniques especially become important as one considers real traffic that is bursty [5 7] which places more stringent demands on packet switches than the usual random (Bernoulli) traffic models. 3. Growable Switch Architecture A Growable Switch Architecture [8 11] has been shown previously to yield optimal delay throughput performance for arbitrary traffic patterns when scaled to arbitrarily large sizes. It consists of a front end memoryless Cell Distribution Network and a column of Output Packet (ATM) Switch Modules (see Fig. 1) The N outputs are divided ....

K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A Growable Packet (ATM) Switch Architecture: Design Principles and Applications," IEEE Trans. Comm., Vol. 40, No. 2, February 1992, pp. 423-430.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," in Proc. IEEE GLOBECOM'89, Dallas, TX, Nov. 1989, pp. 1159--1165.

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K. Y. Eng, M. J. Karol, and Y.-S. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," IEEE Trans. Commun., vol. 40, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and application," IEEE Trans. Commun., vol. 40, no. 2, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and application," IEEE Trans. Commun., vol. 40, no. 2, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y.-S. Yeh, "A growable packet (ATM) switch architecture: Design principles and applications," IEEE Trans. Commun., vol. 40, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and application," IEEE Trans. Commun., vol. 40, no. 2, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and application," IEEE Trans. Commun., vol. 40, no. 2, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: Design principles and application," IEEE Trans. Commun., vol. 40, no. 2, pp. 423--430, Feb. 1992.

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K. Y. Eng, M. J. Karol, and Y. S. Yeh, "A growable packet (ATM) switch architecture: design principles and applications," IEEE Trans. Commun., vol. COM-40, no. 2, pp. 423-430, Feb. 1992.

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Kai Y. Eng, et al., "A Growable Packet (ATM) Switch Architecture: Design Principles and Applications," IEEE Trans. on Commun., vol. 40, no. 2, pp. 423-429, Feb. 1992.

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