D. D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, "System Design Methodologies: Aiming at the 100 h Design Cycle", IEEE Trans. on VLSI Systems, vol. 4, pp 70-82, March 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....A. Hemani, B. Svantesson, P. Ellervee, A. Postula, J. berg, A. Jantsch, H. Tenhunen, High level Synthesis of Control and Memory Intensive Communication Systems , In Proc. of the 8th Annual IEEE International ASIC Conference and Exhibit (ASIC 95) pp 185 191, Austin, Texas, Sept. 18 22, 1995. [15] B. Svantesson, A. Hemani, P. Ellervee, A. Postula, J. berg, A. Jantsch, H. Tenhunen, Modelling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics , In Proc. of the 13th NORCHIP Conference (NORCHIP 95) pp 115 122, Copenhagen, Denmark, Nov. 7 8, 1995. 16] B. ....

....designs are evaluated. If the design does not meet the performance requirements the specification is changed and another design space exploration is performed. This process is iterated until an acceptable solution is found. Such a methodology is termed specify explore refine methodology [15]. Design space exploration is a complex task in general, but can be more manageable in a specific application domain 1.4. High Level Synthesis High Level Synthesis [10, 11, 12] is the task of translating a description of a design at the algorithmic level and translate it into a Register Transfer ....

D. D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, "System Design Methodologies: Aiming at the 100 h Design Cycle", IEEE Trans. on VLSI Systems, vol. 4, pp 70-82, March 1996.

....Figure 2. How model continuity is currently lacking in current COTS MP SDM. 3. THE SER SDM OF GAJSKI, VAHID et al. Gajski, Vahid, et al. developed a hardware software codesign methodology appropriate to their application domain, along with associated system design language with supporting tools [1, 2], which they called Search Explore Refine (SER) Their methodology is similar to describe and synthesize, except that the requirements specification is captured in an executable language called SpecCharts, which they developed. Their methodology raised the level of abstraction in an attempt to ....

.... at most a single processor) differs from ours (streaming input data transformational radar signal processing applications using parallel and distributed processing) But, the design objects we use are logical extensions of those considered by Gajski, Vahid, et al. See Table 1 (after Figure 1 in [1]) for how we have extended this table to include the COTS MP board level hardware (in italics) used in our domain. The SER methdology is shown in Figure 3 (after Figure 2 in [1] along with how we ve extended it to our domain ( Board level SER ) A Novel Codesign Methodology for Real Time ....

[Article contains additional citation context not shown here]

D. D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, and P. Fung, "System Design Methodologies: Aiming at the 100 h Design Cycle," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, pp. 70-82, 1996.

....instances. To guide the search process, it uses both critical path information and the suitability of a node to hardware or software. For example, bit manipulations are better suited to hardware while random accesses to a data structure are better suited to software. Vahid, Gajski et al. 95] [114] perform graph based partitioning of a variable grained specification. The specification language is SpecCharts, a hierarchical model in which the leaves are states of a hierarchical Statecharts like finite state machine. These states can contain arbitrarily complex behavioral VHDL processes, ....

D. D. Gajski, S. Narayan, L. Ramachandran, and F. Vahid, "System design methodologies: aiming at the 100 h design cycle," IEEE Trans. on VLSI, vol. 4, no. 1, Mar. 1996.

.... system designer do his work, all the way from requirements specification through design and on into implementation and production [5] The set of specific tasks, the particular order in which they are executed, and a set of CAD tools to be used during the execution of each task form a methodology [6]. More specifically, a methodology is a coherent set of methods and tools to develop, maintain, and analyze a system at a given stage in its specification and or design [7] The tools are important, but only insofar as they can adequately support the relevant method. Conversely, a method or ....

....between methodology and tool(s) Methodologies infer tool requirements, and tools, at least in part, implicitly infer methodologies. In designing such complex systems, achieving correct functionality is far more important and difficult than minimizing board count or program memory size [6, 8]. Clear and correct encapsulation of requirements in the specification phase has been clearly shown to drastically reduce design and development errors. Also, the earlier such errors are detected, the less expensive they are to correct. A good specification methodology will effectively capture the ....

[Article contains additional citation context not shown here]

D. D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, and P. Fung, "System Design Methodologies: Aiming at the 100 h Design Cycle," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 4, pp. 70-82, 1996.

.... in several papers and books [McF90, Gaj92] System level synthesis, including hardwaresoftware codesign, also are premier design and CAD research topics [Wol94] The most relevant system research subdomain is hardware software partitioning, where a great variety of techniques have been proposed [Bar94, Gaj94, Gup93, Ism94, Gaj96]. Hard real time scheduling efforts has been an important topic of research for three decades. The early work on scheduling of a set of periodic tasks with strict timing constraints on periodicity, arrival and required time of each task, culminated in a classic rate monotonic scheduling algorithm ....

D.D. Gajski, S. Narayan, L. Ramachandran, F. Vahid and others: "System design methodologies: aiming at the 100 h design cycle", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.4, No.1, pp. 70-82, March 1996.

....and then waits for the receiver to assert its own ready signal. In [3] a codesign methodology is discussed using process communication primitives that allow three types of process interaction: synchronized data transfer, unsynchronized data transfer and synchronization without data transfer. In [4], a system design methodology is discussed using abstract send receive channels for communication. In all of these approaches, OOCL can be used to encapsulate the communication using send receive primitives, while implementing the protocol, without any modification to the C or VHDL languages. ....

D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, and P. Fung, "System design methodologies: Aiming at the 100 h design cycle," IEEE Transactions on Very Large Scale Integration Systems, vol. 4, no. 1, pp. 70--82, 1996.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC