A. J. Martin. The Design of a Self-timed Circuit for Distributed Mutual Exclusion. In Proceedings of the 1985.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....failed to find a considerably better ordering in a reasonable amount of time. The proof that the multiplier is finished after a finite number of steps involves the verification of a simple liveness property which can be checked instantly both with BDD based methods and bounded model checking. In [25] an asynchronous circuit for distributed mutual exclusion is described. It consists of n cells for n users that want to have exclusive access to a shared resource. We proved the liveness property that a request for using the resource will eventually be acknowledged. This liveness property is only ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on Very Large Scale Integration, 1985.

....than NuSMV; the Global specification shows the same trend less dramatically. We only see a exponential improvement for After with the Fixpoint encoding: with the SNF encoding, the trend appears to be towards NuSMV being faster. 5. 2 Mutual Exclusion The distributed mutual exclusion circuit from [10] forms a good basis for compar ing the performance of different encodings as it meaningfully implements several specifications. We look at three here, applied to a DME of four elements: Accessibility: if an element wishes to enter the critical region, it eventually will. We check the ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245-260. Computer Science Press, 1985.

....than NuSMV; the Global speci cation shows the same trend less dramatically. We only see a exponential improvement for After with the Fixpoint encoding: with the SNF encoding, the trend appears to be towards NuSMV being faster. 5. 2 Mutual Exclusion The distributed mutual exclusion circuit from [10] forms a good basis for comparing the performance of di erent encodings as it meaningfully implements several speci cations. We look at three here, applied to a DME of four elements: Accessibility: if an element wishes to enter the critical region, it eventually will. We check the ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245-260. Computer Science Press, 1985.

....examples are the synchronous bus arbiter (syncarb) 26] the mutual exclusion element (mutex ) the counter circuit (counter ) and a 3 stage synchronized pipeline (periodic) which are all from the SMV package. Our asynchronous examples include the distributed mutual exclusion (dme) circuit [27, 28, 26], the pausible clock interface (pci) 29] the asynchronous differential equation solver [29] with its estimated version (diffeq est) and its back annotated version (diffeq bka) both of which were analyzed symbolically for their average performance in [12] and finally the asynchronous FIFO circuit ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, 1985.

....latter place is equivalent to coverability of the set. 4. Application example We now consider a more realistic example than the dining philosophers a speedindependent [13] circuit designed to implement a distributed mutual exclusion (DME) protocol. The circuit was designed by Alain Martin [8] and has been analyzed using an abstracted trace theoretic model by Dill [4] Networks of logic gates in speed independent circuits are readily modeled by Petri nets. A network of n gates can be modeled by a Petri net of O(n) places. When we model a network of gates as a Petri net, we introduce ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor,

.... 3 Examples In this section, we look at the performance of the SMV symbolic model checker for two hardware examples a synchronous fair bus arbiter, and an asynchronous distributed mutual exclusion ring circuit (the one studied by David Dill in his thesis [Dil89] and designed by Alain Martin [Mar85]) 3.1 Synchronous arbiter The synchronous arbiter circuit is an example of a synchronous nite state machine. It is composed of a daisy chain of arbiter cells depicted in Figure 2. Under normal operation, the arbiter grants the bus on each clock cycle to the requester with the highest ....

....step of each individual process. Using this fact, we can avoid computing the transition relation of the system and instead use only the transition relations of the individual processes. Our example of an asynchronous state machine is the distributed mutual exclusion (DME) circuit of Alain Martin [Mar85]. It is a speed independent circuit and makes use of special two way mutual exclusion circuits as components. Figure 5 is a diagram of a single cell of the distributed mutual exclusion ring (DME) The circuit works by passing a token around the ring, via the request and acknowledge signals RR and ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on Very Large

....properties for a sequential shift and add multiplier and finding short counterexamples for liveness properties of an asynchronous circuit could be done much faster with SAT than with BDD based methods. In particular, we studied the design of an asynchronous circuit for distributed mutual exclusion [9]. We introduced a bug by removing some fairness constraints. The buggy design violated the liveness property that a request for a resource will be eventually acknowledged, and there is a counterexample of length 2. We applied model checkers to find the counterexample. Table 1 shows the results of ....

MARTIN, A. J. The design of a self-timed circuit for distributed mutual exclusion. In Proceedings of the 1985 Chapel Hill Conference on Very Large Scale Integration (1985), H. Fuchs, Ed.

....of them. The CTL formula was translated to an #fi#zz automaton, and the conventional implicit method and the proposed partially explicit method were applied. A typical example of checked properties was AB, where B is shown in Fig. 8. 5.2. 2 DME circuits Distributed mutual exclusion(DME) circuit [9] is composed of identical arbiter cells, and each user accesses to the resource exclusively by request or acknowledge signals. Each logic gate in a cell is modeled as afi45z state machine to havefi##z delays of arbitrary length [10] A user module is attached to each cell. When ack is low, the ....

A.J. Martin, "The design of a self-timed circuit for distributed mutual exclusion," Proc. 1985 Chapel Hill Conference on Very Large Scale Integration, 1985.

....language level (DC) down to hardware implementation. Previous work using transformation algebra was pursued by He Jifeng et al. e.g. 7] The broader framework of our work is given by [6, 12] As a complementary approach one might regard the self timed circuit implementation techniques as in [1, 10, 11]. An approach which also takes several levels of abstraction into account and is based on a modal, in their case intuitionistic logic is presented in [2] They are, however, not interested in transformational construction, and their modal logic serves for the purpose of abstracting from ....

A.J.Martin. The design of a self-timed circuit for distributed mutual exclusion. In: H.Fuchs, Ed., Proc 1985 Chapel Hill Conference VLSI, 1985, 247--260.

....[Mart89] Mart90] and Burns [Burn87] have developed compileroriented techniques for the translation of specifications expressed in CSP into four phase delay insensitive circuits. Their techniques have been used to develop CHAPTER 5. MODELLING ASYNCHRONOUS SYSTEMS 111 a number of circuits [Mart85] [Mart85a] [Mart85b] including a complete asynchronous microprocessor [Mart89a] Mart89b] Akella and Gobalakrishan have extended Martin s work in a system called Shipha [Akel91] Gopa93] which also employs a CSP based notation but allows global shared variables. Van Berkel s group at Philips Research ....

Martin, A. J., "The design of a Self-timed circuit for Distributed Mutual Exclusion", Proceedings of the 1985 Chapel Hill Conference on VLSI, Computer Science Press, 1985., pp. 247-260.

.... of an n way arbiter using 2 way elements (this illustrates the use of eager witnesses, and efficiency of the heuristic for hierarchical reduction) 3) a leader election protocol (illustrating the efficiency of the hierarchical reduction) and (4) ring of distributed mutual exclusion cells [20] (illustrating use of automatic witness construction, assume guarantee proofs, and hierarchical reduction) While these examples have been analyzed previously by model checkers, prior studies have focussed on verifying temporal logic requirements, and in contrast, our tool checks (stutter closed) ....

....no private variable in Spec, we can directly check if System Spec. The result is shown in Figure 7, which indicates effectiveness of the hierarchical reduction (see Figure 6 for clustering for the hierarchical reduction) 6. 3 Distributed mutual exclusion In Distributed Mutual Exclusion (DME) [20], a ring of cells are connected to a user process each. Figure 8 shows the specification of a cell. In the specification, a virtual token is passed around the cells clockwise. Initially, only one cell has the token. Each cell can send requests to its right neighbor (right req) and ....

A. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Chapel Hill Conference on Very Large Scale Integration, pp. 245--260, 1985.

....g 2 ) will be active at any time. If the circuit goes into metastability, both outputs will remain low until the metastable state is resolved. g 1 r 1 r 2 g 2 ME Figure 4.22: Mutual Exclusion Element. Two types of 4 phase n way arbiters have been the focus of most published work. Martin [47], Ebergen [23] and Ebergen et al. 22] have worked on token ring arbiters, formed by a linear chain of modules that circulate a special token, the authorization to grant requests. Seitz [81] Yakovlev et al. 101] and Josephs et al. 38] have presented designs for tree arbiters, formed by ....

Alain J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245--260. Computer Science Press, 1985. 158

....designer proves the system is an implementation of the specification. In this first transformation step, the designer may apply the tools of concurrent program development and verification. The concurrent program is then transformed into a semantically equivalent self timed circuit. Alain Martin[5, 7] describes a general framework for performing these transformation. In this thesis, we describe a way of automating the compilation procedure. The final task is the realization of the operator sets in a computing medium such as a VLSI chip. One approach is to implement each operator as a CMOS ....

....as parameters. No variables or ports may be inherited from the surrounding scope when these code segments are instantiated. We illustrate the instantiation mechanism with a complete example (see Figure 1. 6) a ring of four processes which insures mutually exclusive access to a single resource[7]. The process ring is created by instantiating three priv0 processes and one priv1 process. The L and R ports are connected via channels to form a ring of four elements. The four ports U0; U1; U2; U3 connect to the environment. 8 passive U; L active R boolean b = false procedure P [b Gamma ....

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A. J. Martin, "The Design of a Self-Timed Circuit for Distributed Mutual Exclusion", Proc. 1985 Chapel Hill Conf. VLSI, ed. Henry Fuchs, pp 247-260 (1985)

....be enlarged by simply increasing the number of instances of the basic cells. However, their intrinsic regularity has not been exploited to verify the circuit. The examples used are the following: master read (obtained from automatic synthesis tools) a Distributed Mutual Exclusion (DME) circuit [8, 5], a tree arbiter [15] an asynchronous FIFO [9] a register file [12] and a demultiplexer [2] Results on flat (no reduction to complex gates) and hierarchical verification are shown 4 . The 4 For the DME, results are comparable to those presented in [3] when multiple initial states are used. ....

Alain J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, Proc. of the Chapel Hill Conf. on VLSI, pages 245--260. Computer Science Press, 1985.

....variables of M gives the set of states where the formula f holds. Note that our approach makes it unnecessary to modify SMV (or even understand how SMV is actually implemented) We have evaluated the approach on several standard SMV programs (including Martin s distributed mutual exclusion circuit [15] and the synchronous arbiter described in McMillan s thesis [16] In order to make sure that the experiments were unbiased, we deliberately chose specifications which could be expressed in both CTL and LTL. The results that we obtained were quite surprising. For the examples we considered, the ....

....symbolic LTL model checking. In order to compare the performance of LTL model checking with CTL model checking, we used two sequential circuit designs whose specifications can be described in both LTL and CTL, The first example is a distributed mutual exclusion(DME) circuit designed by Alain Martin[15]. The DME circuit is a speed independent token ring, which consists of identical arbiter cells. A user of the DME circuit obtains exclusive access to the resource via request and acknowledge signals. We assume aribitrary delay for all gates in the circuit. Each gate is modeled as a finite state ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on Very Large Scale Integration, 1985.

....quadratically with depth when we use the abstract model of the control part of each cell. 8.3 Distributed Mutual Exclusion As another example, we considered the verification of an asynchronous circuit for ensuring mutually exclusive access to a shared resource. This circuit is also due to Martin [27, 23]. The circuit consists of a ring of c cells. Each cell communicates with a user of the resource and with its left and right neighbors in the ring. Mutual exclusion is ensured by having a single token that is passed around the ring. A cell must have the token before granting access to its user. ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Chapel Hill Conference on VLSI, 1985.

....several methodologies that generate functional asynchronous circuits under various timing assumptions have been developed (for example, 10, 35, 12, 45, 39] In particular, the Caltech approach, invented by A. J. Martin [30] has produced many successful CMOS circuits such as stacks, arbiters [27], routers, a 3x 1 special purpose processor [19] a multiply accumulator [40] a memory management unit [38] and, in 1988, the first asynchronous microprocessor [32] The favorable statistics of the microprocessor [33] and its portability to gallium arsenide technology [43] have contributed to ....

A.J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs, editor, 1985 Chapel Hill Conference on VLSI , pp. 247-260, Computer Science Press, Rockville, MD, 1985.

....1. 16x16 bit sequential shift and add multiplier with overflow flag and 16 output bits (sec = seconds, MB = Mega Byte) to prove the recurrence diameter (see Definition 22) to be jrj. This took only very little time compared to the total verification time and is shown in the column diameter . In [13] an asynchronous circuit for distributed mutual exclusion is described. It consists of n cells for n users that want to have exclusive access to a shared resource. We proved the liveness property that a request for using the resource will eventually be acknowledged. This liveness property is only ....

A. J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on Very Large Scale Integration, 1985.

....algorithms on a Sun SPARCstation 10, with 64Mb of memory. Notice that for large designs the complete set of states has not been explicitly calculated (denoted by in the tables) 7. 1 Distributed Mutual Exclusion (DME) arbiter The first example is a ring of N DME cells and it is due to Martin [Mar85] It has also been studied by several authors ( Dill [Dil88, DC86] McMillan [McM92] Burch [BCL 92] with different approaches. Figure 8.a shows a ring with two users with a mutually exclusive access to the resource, while Figure 8.b shows the Petri describing the behavior of that circuit. ....

Alain J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Chapel Hill Conference on VLSI, 1985.

....These circuits are designed to function correctly regardless of the internal delays of the operators. The required operator types include the combinational elements, WIRE, AND, and OR; and the state holding elements shown in Figure 2. Each operator is defined in terms of a set of production rules[4, 5]. A production rule is a simple transition rule of the form G 7 Gamma S, where G is a boolean expression and S is an assignment to true or false. All references to a circuit variable are assumed to have the same value (isochronic forks) 1, 4] A synchronizer, which cannot be represented in terms ....

....translated into this language are written in a different typeface than source language programs. This distinction is not necessary, but serves as an aid in describing which syntactic forms have already been or have yet to be translated. For compatibility with the notation of previous papers[4, 5], we use overlines to denote probes (X) and up and down arrows to denote assignment (x ; x#) 3.3 Compilation of the Basic Constructs Figure 3 displays all of the basic processes produced by the program transformations described in the next chapter. The remaining step is to compile these basic ....

[Article contains additional citation context not shown here]

A.J. Martin, "The Design of a Self-Timed Circuit for Distributed Mutual Exclusion ", Proc. Chapel Hill Conf. VLSI, ed. H. Fuchs, pp 247--260 (1985)

....size without the hazards associated with clock distribution in large synchronous designs. In this paper, we present a mechanical method for transforming a concurrent program into a semantically equivalent self timed circuit. This method is based on the manual circuit compilation techniques of [6, 8], but the translation mechanism follows standard syntax directed techniques. We describe the necessary translation rules and apply these to an example. This transformation method allows any program in the source language to be compiled into a self timed circuit, and further 1 in Advanced ....

.... [ b B: 0 Y(0) 1 Y(1) 2 Y(2) b down ] process arbiter(A,B,Y) Figure 3: Programs for the Switch and Arbiter Processes tional operators WIRE, AND, and OR; and the state holding operators shown in Figure 4. Each operator is defined in terms of a set of production rules[6, 8]. A production rule is a simple transition rule of the form G 7 Gamma S; where G is a boolean expression and S is an assignment to true or false. All references to a circuit variable are assumed to have the same value (isochronic forks) 2, 6] A synchronizer, which cannot be represented in terms ....

[Article contains additional citation context not shown here]

A.J. Martin, "The Design of a Self-Timed Circuit for Distributed Mutual Exclusion," Proc. 1985 Chapel Hill Conf. VLSI, ed. Henry Fuchs, pp 247-260 (1985)

....region. Figure 19: A D element implemented with lopsided gates. Figure 20: Martin s DME circuit, as verified by Dill. Borrwed from [Dil88b] Page 63. in [Dil88b] complete with an important correction. The construction of the circuit, in its earlier, uncorrected, form can be found in [Mar85]. In order to implement the DME we need a few extra primitives that use an NRZ interface (see Figure 21. Part (a) shows the an NRZ SR latch, Part (b) shows an NRZ double C element. The NRZ SR latch has NRZ inputs for s and r and NRZ outputs for dt and df (the stored data and inverted ....

Alain J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In 1985 Chapel Hill Conference on Very Large Scale Integration, 1985, pages 245--260. (The resulting circuit has a bug, a corrected version appears in [Dil88b].)

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A. J. Martin. The Design of a Self-timed Circuit for Distributed Mutual Exclusion. In Proceedings of the 1985.

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A.J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs and W.H. Freeman, editors, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245--260, New York, 1985.

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A.J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In H. Fuchs and W.H. Freeman, editors, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245--260, New York, 1985.

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