T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer, Jan. 1998.  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... of specialized configuration optimization techniques (such as fixed objective scheduling and allocation) which are already in abundance in the literature (e.g. see [11] for a survey) Our work is complementary to such existing efforts and also to work on multiprocessor system synthesis [1][2], which can be used to derive the store ofpre computed configurations that is input to the techniques developed in this paper. 2. Problem formulation A set of relevant metrics, such as latency, throughput, average power, peak power, and number of resources, is denoted by M. Ifa certain metric ....

....[ ml, Cl) m2, c2) inK, CK) mR] stack output goal, constraint, objective goal g S.push(m R) push( c K) g = ml, el) m2, c2) mK 1, CK 1) mK] return (g , CK , mK ) Fig. 3. Definition of functions promoteConstraint and demoteConstraint from Figure 2. 10 problem [2, 8], as shown in [9] For the simple case of a two dimensional goal space, a polynomial time approximation algorithm with a 3 approximation factor exists for the k median problem [2] Configuration management problems P1 and P2 can be viewed as extreme cases in the sense that in one of them we want ....

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T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Journal of Design Automation for Embedded Systems, 3(1):23-58, 1998.

....peak and quiescent power metrics are incorporated into the cluster allocation phase of COSYN LP. For details, we refer the reader to [18] 4. 3 CodeSign As part of the CodeSign project at ETH Zurich, Blickle, Teich, and Thiele have developed a search technique for hardware software cosynthesis [13] that is based on the framework of evolutionary algorithms. In evolutionary algorithms, complex search spaces are explored by encoding candidate solutions as chromosomes, and evolving populations of these chromosomes by applying the principles of reproduction (retention of chromosomes in a ....

....it is similar to the application graph concept defined in Section 3.1. However, it is slightly different in its incorporation of special communication vertices that explicitly represent inter actor communication, and are ultimately mapped onto communication resources in the target architecture [13]. The remaining dependence graphs specify different levels of abstraction or refinement during implementation. For example, a dependence graph could specify an architectural description consisting of available resources for computation and communication (architecture graph) and another ....

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T. Blickle, J. Teich, and L. Thiele, "System-level Synthesis using Evolutionary Algorithms," Journal of Design Automation for Embedded Systems, pp. 23-- 58, 1998.

....speed versus cost, power, etc. from which he she may decide to choose and re ne one solution to the nal product. In this area, multiobjective optimization problems have to be solved. An approach that uses evolutionary algorithms for design exploration of Pareto optimal fronts can be found in [1] for system level synthesis (a generalization of hardware software partitioning) or for optimal code synthesis for DSP processors from data ow graphs [4] 6] 5] Unfortunately, existing tools are either too specialized to be used for di erent synthesis problems, too tightly coupled to tools ....

....Design Space Exploration During High Level Synthesis Note that the following example of high level synthesis is just one example where the above concepts have been applied sucessfully in the context of embedded system synthesis. Others are hardware software partitioning (system level exploration) [1] and the automatic exploration of task mappings in the context of massively parallel processor arrays. 5.1 Problem speci cation The work ow of the exploration process using EXPLORA will be demonstrated by the synthesis of a single chip embedded system design based on behavioral VHDL with an FPGA ....

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T. Blickle, J. Teich, and L. Thiele. System-level synthesis using Evolutionary Algorithms. J. Design Automation for Embedded Systems, 3(1):23-58, January 1998.

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T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer, Jan. 1998.

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T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In Rajesh Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer Academic Publishers, Boston, January 1998.

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T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer Academic Publishers, Boston, Jan. 1998.

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Blickle, T., Teich, J., Thiele, L.: System-Level Synthesis Using Evolutionary Algorithms. In Gupta, R., ed.: Design Automation for Embedded Systems. Number 3. Kluwer Academic Publishers, Boston (1998) 23--62

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T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer, Jan. 1998.

No context found.

T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer Academic Publishers, Boston, Jan. 1998.

No context found.

T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer Academic Publishers, Boston, Jan. 1998.

No context found.

Blickle, T., Teich, J., Thiele, L.: System-Level Synthesis Using Evolutionary Algorithms. In Gupta, R., ed.: Design Automation for Embedded Systems. 3. Kluwer Academic Publishers, Boston (1998) 23--62

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Blickle, T., Teich, J., Thiele, L.: System-Level Synthesis Using Evolutionary Algorithms. In Gupta, R., ed.: Design Automation for Embedded Systems. 3. Kluwer Academic Publishers, Boston (1998) 23--62

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T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems, 3(1):23--58, 1998.

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T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, 3, pages 23--62. Kluwer, Jan. 1998.

....approach to the HW SW partitioning problem which has been inplemented in a tool named SSEA . This tool was conceptualized and implemented by T. Blickle, J. Teich, and L. Thiele at the ETH Zurich [40] and developed further by J. Teich at the University of Paderborn and E. Zitzler at ETH Zurich [39, 3]. The design space exploration is based on multi objective cost functions, hence for the system level synthesis of embedded systems. The user inputs a directed problem graph (e.g. a task graph) GP = VP ; EP ) which may be either acyclic or cyclic, e.g. an iterative problem graph with weights ....

....allocations and feasible bindings in order to restrict the combinatorial search space. De nition 6 (Feasible Allocation) A feasible allocation is an allocation that allows at least one feasible binding . Theorem 7 (Feasible Binding) The determination of a feasible binding is NP complete [39, 3]. The proof may be found in [39, 3] Finally, it is necessary to de ne a schedule. Let delay(v; denote the (estimated) execution time of the operation associated to node v of the problem graph GP ( G 1 ) In order to be as general as possible at this point, we suppose that the execution time ....

[Article contains additional citation context not shown here]

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using Evolutionary Algorithms. J. Design Automation for Embedded Systems, 3(1):23-58, January 1998.

....the design of a family of Set Top boxes is proposed. 1. Introduction Designing a system to best meet a set of requirements on cost, speed, power, etc. for a given, single application is challenging, but has been formalized already by means of graph based allocation and binding problems such as [2]. Such graphical mapping models found acceptance also in commercial systems such as [3] In areas such as platform based design, however, a system should be dimensioned such that it is able to implement not only one particular application optimally, but instead a complete set of different ....

....the implementation side, i.e. systems that change their structure over time. With this model, we are then able to define the problem of dimensioning a system that is able to dynamically switch its behavior and or structure at run time. Basically, this problem extends previous approaches such as [2] to reconfigurable, platform based systems that implement timedependent functionality. Finally, an efficient exploration algorithm for exploring the flexibility cost tradeoff curve of a system under design is presented that efficiently prunes solutions that are not optimal with respect to both ....

[Article contains additional citation context not shown here]

T. Blickle, J. Teich, and L. Thiele. System-Level Synthesis Using Evolutionary Algorithms. In R. Gupta, editor, Design Automation for Embedded Systems, number 3, pages 23--62. Kluwer Academic Publishers, Boston, Jan. 1998.

.... for exploring the design space, one of which is a branch and bound search algorithm where the problem is specified in the form of integer linear equations (see [12] For complicated examples where the design space can be very large, it is possible to use evolutionary search techniques (see [1]) and this is the approach we describe here. As already mentioned, we are faced with a number of conflicting objectives trading cost against performance, and there are also conflicts arising from the different usage scenarios of the processor. We illustrate this in the case study, which involves ....

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems, 3(1):23--58, 1998.

....considered synthesis subproblems like the binding of coarse granular tasks at the systemlevel to either hardware or software (so called hardware software partitioning) Here, bottom up solutions including clustering as top down approaches including greedy strategies have been proposed. In [20] [4], we proposed a formal graph theoretic approach to the generalized synthesis problem the main concepts of which are summarized next. A synthesis specification model consists of three main components: The problem that should be mapped onto an architecture as well as the class of possible ....

....Definition 3.1 (Dependence Graph) A dependence graph is a directed graph G(V;E) V is a finite set of nodes and E (V V) is a set of directed edges. For example, the dependence graph to model the data flow dependencies of a given specification will be termed problem graph G P = V P ; E P ) [4]. Here, V P contains nodes which model either functional operations or communication operations. The edges in E P model dependence relations, i.e. define a partial ordering among the operations. Example 3.1 One can think of a problem graph as the graph obtained from a data flow graph by inserting ....

[Article contains additional citation context not shown here]

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using Evolutionary Algorithms. J. Design Automation for Embedded Systems, 3(1):23-- 58, January 1998.

....either areas a lot of work has been published. In [1] the problem of automatically determining an architecture composed of hardware library components (only connectable via simple ports) using genetic algorithms, simulated annealing and tabu search considering real time constraints is studied. In [3] and [20] a system level synthesis approach using an evolutionary algorithm is described. Its problem and architecture graph descriptions consider communication time and bus conflicts. 6] extends [3] and includes power consumption as an optimization goal. HiPART [14] implements a set of ....

....algorithms, simulated annealing and tabu search considering real time constraints is studied. In [3] and [20] a system level synthesis approach using an evolutionary algorithm is described. Its problem and architecture graph descriptions consider communication time and bus conflicts. 6] extends [3] and includes power consumption as an optimization goal. HiPART [14] implements a set of communicating C and VHDL processes onto a heterogeneous target platform [13] consisting of processor, ASIC, DSP and FPGA modules by using an interactive hierarchical partitioning algorithm. However, the ....

[Article contains additional citation context not shown here]

Tobias Blickle, Jurgen Teich, and Lothar Thiele. System-level synthesis using evolutionary algorithms. Journal on Design Automation for Embedded Systems, 3(8):23--58, January 1998.

.... for exploring the design space, one of which is a branch and bound search algorithm where the problem is specified in the form of integer linear equations (see [11] For complicated examples where the design space can be very large, it is possible to use evolutionary search techniques (see [1]) and this is the approach we describe here. As already mentioned, we are faced with a number of conflicting objectives trading cost against performance, and there are also conflicts arising from the different usage scenarios of the processor. We illustrate this in the case study, which involves ....

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems, 3(1):23--58, 1998.

....memory or data nodes, power consumption, cost functions and bandwidth requirements. It should be obvious that the model can easily be extended. Finally, it may be noted that the above model closely resembles the one that was used for a design space exploration of hardware software architectures in [6]. 3 Modeling Discrete Event Streams and Systems 3.1 Basic Models Traditionally event streams are modeled statistically. Methods that have been applied are well known in the area of queuing theory. However, If we are interested in hard bounds instead of failure probabilities, it is more suitable ....

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems, 3(1):23-58, 1998.

No context found.

T. Blickle, J. Teich, L. Thiele, "System-level Synthesis using Evolutionary Algorithms", Journal of Design Automation for Embedded Systems, pp. 23-58, 1998.

No context found.

T. Blickle, J. Teich, L. Thiele, System-level synthesis using evolutionary algorithms, Design Automation for Embedded Systems, Kluwer Academic Publishers 3 (1) (1998) 23--58.

No context found.

T. Blickle, J. Teich, and L. Thiele. System-level synthesis using evolutionary algorithms. Design Automation for Embedded Systems, Kluwer Academic Publishers, 3(1):23--58, Jan. 1998.

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Blickle T., Teich J., Thiele L., "System-Level Synthesis Using Evolutionary Algorithms", Design Automation for Embedded Systems, 1998, Issue 3, Page(s): 23-58.

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