F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM Workshop on Language, Compiler, and Tool Support for Real-Time Systems, 137{ 145, 1995.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....This cache related pre emption delay (CRPD) or cache refill penalty that can be considered as an indirect cost is illustrated in figure 1 and 8. The CRPD can be eliminated or reduced by partitioning the cache so each task has a private part of it, but to the price of decreased over all performance[12, 13, 14]. Continuously measuring cache performance. By continously monitoring the cache miss ratio, maximum and average miss ratio during a time slice can be determined. If the time slice is smaller than T 1 T 2 without pre emption T 1 T2 preempts T1 T1 cont. Cache refill penalty = CRPD with ....

Frank Mueller. Compiler support for softwarebased cache partitioning. In ACM SIGPLAN Workshop on Languages, Compilers and Tools for RealTime Systems, La Jolla, CA, USA, June 1995.

....interference. Allowing this separation has the knock on effect of improving the predictability and determinism of the cache. The idea of exposing the cache to the programmer has been proposed before [19] and has been investigated by Juan et al. 10] Kirk [11] Jain et al. 9] and Mueller [16]. The most obvious deficiency of most these systems, is the inflexible manner in which cache partitions are allocated and the questionable approach of using entirely hardware or software based designs. These techniques lack interaction from the one component, the compiler, that enables them to ....

F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137--145, June 1995.

....running the kernels concurrently, the partitioned cache can sustain high performance while the conventional caches suffer a significant drop. 5 Related and future work The idea of exposing the cache to the compiler or programmer is not new. It has been proposed before by, amongst others, Mueller [12], Wagner [16] Kirk [7] and Juan [6] Our partitioned cache system benefits over these systems by using a combination of hardware and software to attack the problem. This allows the cache to deliver features such as fine grain, per object reference partitioning, which would be costly under a ....

....cache system benefits over these systems by using a combination of hardware and software to attack the problem. This allows the cache to deliver features such as fine grain, per object reference partitioning, which would be costly under a software only system like that proposed by Mueller [12] (that discusses partitioning on a priority basis) and simple hardware logic, that is hard in an unassisted, hardware only system like Wagners [16] Kirk [7] describes a system that partitions on a per task basis, this offers no inter object interference removal within a task achieved with our ....

F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137-- 145, June 1995.

....of data parallel programs. The issues examined in these partitioning are how to efficiently distribute and align data across processors so as to achieve a workload balance and reduce interprocessor communication. Some of the other typical uses of data partitioning are to enhance cache performance [7]. Wolf and Lam [11] have focussed on data locality of a loop nest in parallel programs, by transforming the code via interchange, reversal, skewing and tiling to minimize memory latency. Data partitioning on memory scarce embedded devices is a challenging problem mainly due to a very limited ....

F. Mueller. Compiler support for software-based cache partitioning. In Workshop on Languages, Compilers and Tools for Real-time Systems, June 1995.

....loops is improved, we expect that we will be able to extend our partitioning to other parts of the memory hierarchy, including multi level caches and virtual memory. The idea of exposing the cache to the compiler or programmer is not new. It has been proposed before, by, amongst others, Mueller [10], Wagner [11] Kirk [12] and Juan [13] The microcache system benefits from using a combination of hardware and software to attack the problem. This allows the microcache to deliver features such as fine grain, per object reference partitioning, which would be costly under a software only system ....

....Juan [13] The microcache system benefits from using a combination of hardware and software to attack the problem. This allows the microcache to deliver features such as fine grain, per object reference partitioning, which would be costly under a software only system like that proposed by Mueller [10] (that discusses partitioning on a priority basis) and simple hardware logic, that is hard in an unassisted, hardware only system like Wagners [11] Kirk [12] describes a system that partitions on a per task basis, this offers no inter object interference removal within a task achieved with our ....

F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp 137--145, Jun 1995.

....or register allocation and not on data segment partitioning. Data partitioning has been extensively examined in parallel computing focusing on the issues of data alignment and interprocessor communication [13] Some of the other typical uses of data partitioning are to enhance cache performance [8]. Wolf and Lam [12] have achieved data locality of a loop nest in parallel programs, by transforming the code via interchange, reversal, skewing and tiling to minimize memory latency. Data partitioning on memory scarce embedded devices is a challenging problem mainly due to a very limited amount ....

Frank Mueller. Compiler support for software-based cache partitioning. In Workshop on Languages, Compilers and Tools for Real-time Systems, June 1995.

....communication. Some data partitioning optimizations in parallel computing also focus on file I O. The aim is to decrease the number of file I O s and communications between processors that required for I O [3] Some of the other typical uses of data partitioning are to enhance cache performance [8]. Wolf and Lam [12] have focussed on data locality of a loop nest in parallel programs, by transforming the code via interchange, reversal, skewing and tiling to minimize memory latency. Data partitioning on memory scarce embedded devices is a challenging problem mainly due to a very limited ....

F. Mueller. Compiler support for software-based cache partitioning. In Workshop on Languages, Compilers and Tools for Real-time Sy stems, June 1995.

....an addition to an existing machine, we view it as an integrated part of the system. Instead of adding features to a cache that improve average performance at the expense of predictability (such as a victim cache [3] we argue that we should simplify our cache model and expose it to the compiler [4, 5, 6]. In the rest of this paper we shall first outline why caches are unpredictable in Section 2, before presenting a predictable hardware partitioned cache with compiler support in Section 3. Preliminary results that support our argument are presented in Section 4. 2 Why are caches unpredictable ....

....In the example above, the shift will be 0 for the stride of 1, and the shift will be 16 for the stride of 100. Notice that all the information above is automatically derived by the compiler. There is no user intervention in this process. In this respect our approach differs from that of Mueller [5] and Wagner [6] who also describe partitioned caches, but require the programmer to manage the partitions. 3.1.1 The hardware software interface On every memory operation, the processor must pass three values to the cache system: the partition base address, the partition size, and the shift value ....

F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp 137--145, June 1995.

....unattractive in non real time systems, real time designers worried about WCET view it as a significant improvement. This article analyzes two fundamental methods of managing caches for predictable behavior. The two methods are software based and have been presented previously in the literature [12, 9]. We quantitatively compare the policies by leveraging an existing analytical cache model in a novel manner that allows exploration of system performance across a wide range of designs. Although currently limited to systems with a single level of cache, this analysis reveals that cache policy ....

....for predictable cache behavior. The first method relies on dividing the cache into distinct partitions and the other restricts where context switches can occur. Kirk and Strosnider [6] detail a hardware design for the MIPS R3000 that allows a cache to be partitioned among processes. Mueller [9] implemented a compiler that partitions the cache strictly through software, via positioning of code. On the other hand, the Spring Real Time System [12] controls where context switches can occur using a software technique that defines regions of code during which interrupts are masked. By ....

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Frank Mueller. Compiler Support for Software-Based Cache Partitioning. ACM Sigplan Workshop on Languages, Compilers and Tools for Real-Time Systems, pages 125--133, June 1995.

....is aimed at improving the cache predictability by annulling the extrinsic interference by providing each task with a private cache partition. Additionally, a common partition may be used for data sharing and non critical tasks. The cache partitioning approach may be implemented by software [25][18] or hardware [11] 9] 12] 10] The hardware schema requires the cache be off chip and some additional external circuitry for cache control. It introduces added latency to the processor cycle. The software solution requires compiler support. The application code is relocated to provide exclusive ....

F. Mueller."Compiler Support for Software-Based Cache Partitioning". Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, La Jolla, CA, June 1995.

....loops properly, we expect that we will be able to extend our partitioning to other parts of the memory hierarchy, for example multi level caches and virtual memory. The idea of exposing the cache to the compiler or programmer is not new. It has been proposed before, by, amongst others, Mueller [13], and Wagner [14] Most of the partitioned caches are software based, for example the work by Mueller. We propose to implement our partitioning in hardware as opposed to software techniques in which a compiler is used to stripe code and data throughout the process image. Our implementation offers ....

F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp 137--145, June 1995.

....to improve data cache performance when a large array conflicts with itself. Placement optimizations have been used to reduce false sharing in shared memory multiprocessors [16] Compilerdirected variable partitioning has been proposed as an approach to reduce inter variable interactions [27] for the purpose of improving the predictability of cache access latencies in real time systems. The Scout operating system [25] employs data placement to reduce data cache conflict between active protocol stacks. Many parallels to this work can be found in software techniques developed for ....

F. Mueller. Compiler support for software-based cache partitioning. ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, 30(11):125--133, June 1995.

....to improve data cache performance when a large array conflicts with itself. Data placement optimizations have been used to reduce false sharing in shared memory multiprocessors [JE95] Compiler directed variable partitioning has been proposed as an approach to reduce inter variable interactions [Mue95] for the purpose of improving the predictability of cache access latencies in real time systems. The Scout operating system [MMO 94] employs data placement to reduce data cache conflict between active protocol stacks. The approach used to name heap variables was adopted from [BZ93] The ....

F. Mueller. Compiler support for software-based cache partitioning. ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, 30(11):125--133, June 1995.

....is aimed at improving the cache predictability by annulling the extrinsic interference by providing each task with a private cache partition. Additionally, a common partition may be used for data sharing and non critical tasks. The cache partitioning approach may be implemented by software [46][30] or hardware [16] 19] 17] 18] The hardware schema requires the cache be offchip and some additional external circuitry for cache control. It introduces added latency to the processor cycle. The software solution requires compiler support. The application code is relocated to provide exclusive ....

F.Mueller. "Compiler Support for Software-Based Cache Partitioning". Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, La Jolla, CA, June 1995.

....to the processor cycle [7] The software solution requires compiler support. The application code is relocated to provide exclusive mappings on the cache for each task. This scheme also introduces delays, in this case due to insertion of branches to interconnect the relocated pieces of code [16]. In addition, the access pattern of data structures must be changed in order to achieve exclusive mappings into the data cache. In [8, 18] an algorithm is presented to optimally allocate partitions to tasks for SMART (Strategic Memory Allocation for Real Time) The figure of merit of the ....

F. Mueller. "Compiler Support for Software-Based Cache Partitioning". Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, La Jolla, CA, June 1995.

....system) cache invalidations and thus unexpected cache misses may occur when the execution of a task is resumed later on. Hardware and software approaches have been proposed to counter this problem but find little use in practice due to a loss of cache performance when caches are partitioned [20, 52, 29, 24]. Recently, attempts have been made to incorporate caching into rate monotone analysis and responsetime analysis [6, 7, 21] which allows WCET predictions for non preemptive systems to be used in the analysis of preemptively scheduled systems. This seems most promising since the information ....

F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137-- 145, June 1995.

....system) cache invalidations may occur resulting in unexpected cache misses when the execution of a task is resumed later on. Hardware and software approaches have been proposed to counter this problem but find little use in practice due to a loss of cache performance when caches are partitioned [11, 22, 16]. Recently, attempts have been made to incorporate caching into rate monotone analysis and response time analysis [3, 4] which may allow WCET predictions for non preemptive systems to be used in the analysis of preemptively scheduled systems. Early work in the field of WCET prediction used a ....

F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137--145, June 1995.

....system) cache invalidations may occur resulting in unexpected cache misses when the execution of a task is resumed later on. Hardware and software approaches have been proposed to counter this problem but find little use in practice due to a loss of cache performance when caches are partitioned [12, 21, 17]. Recently, attempts have been made to incorporate caching into rate monotone analysis and response time analysis [4, 5] which may allow WCET predictions for non preemptive systems to be used in the analysis of preemptively scheduled systems. Early work in the field of WCET prediction used a ....

F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137--145, June 1995.

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F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM Workshop on Language, Compiler, and Tool Support for Real-Time Systems, 137{ 145, 1995.

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F. Mueller. Compiler support for software-based cache partitioning. In Proceedings ACMWorkshop on Languages, Compilers and Tools for Real-Time Systems (LCTES'95), Jun. 1995.

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F. Mueller. Compiler support for software-based cache partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pages 137-145, June 1995. 96

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F. Mueller. Compiler support for software-based cache partitioning. In Proc. of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Real-Time Systems, pages 137--145, La Jolla, CA, USA, June 1995.

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F. Mueller. Compiler Support for Software-Based Cache Partitioning. In ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp 137#145, June 1995.

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