Lee Higbie. Quick and Easy Cache Performance Analysis. Computer Architecture News, 18(2):33--44, June 1990. Home/Search Document Not in Database Summary Related Articles Check |
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Adding Instruction Cache Effect to Schedulability.. - Busquets-Mataix.. (1996) (Correct)
....is presented. In [13] the relationship between associativity and miss ratio is also categorized. A recent paper [35] presents a purely statistical technique based on a so called gap model, to derive the expected number of misses of a given program trace over all possible address mappings. In [12] some formulas based on empirical evidence are presented for a variety of cache configurations. The following formula corresponds with instruction cache. M is the miss rate. The cache size is 2 s bytes. The number of bytes of the cache line is 2 r . A is the architectural factor, usually ....
.... 3 07 075 1 10 2 25 3 3 2 . a Recently some papers have been presented to estimate the WCET of cached programs [23] 21] 29] 3] The last two references propose a static method capable of predicting conservatively around 70 of cache hits. However, we have chosen the model presented in [12] for several reasons. Firstly, it takes into account the factors we intend to include in the experiments in an analytical way. Additionally such a model presents different formulas for instruction, data or mixed caches, which is especially desirable in our experiments, since we are only concerned ....
L.Higbie. "Quick and Easy Cache Performance Analysis". ACM Computer Architecture News, Vol. 12, Num. 2, pages 33-44, June 1990. 15
Hybrid Instruction Cache Partitioning for.. - Busquets-Mataix.. (Correct)
....averagecase miss rates rather than worst case miss rates. The available techniques to obtain the WCET of cached programs deliver miss rates which are very close to average ones. The required level of accuracy for the evaluation allows such an approximation. We rely on the formulae given in [6], which is based on extensive empirical observation, to obtain the miss rates from the cache size, cache line size, and associativity degree. Given the miss rate, it is easy to obtain the stall time based on the cache miss penalty (memory read time) and the number of memory references (MIPS ....
L. Higbie. "Quick and Easy Cache Performance Analysis". ACM Computer Architecture News, Vol. 18, Num. 3, pages 33-44, June 1990.
Early System Analysis of Cache Performance . . . - Roberts (1992) (Correct)
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Lee Higbie. Quick and Easy Cache Performance Analysis. Computer Architecture News, 18(2):33--44, June 1990.
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