R. S. Martin and J. P. Knight. " Power-profiler: optimizing ASICs power consumption at the behavioral level. " In Proceedings of the 32nd Design Automation Conference, pages 42-47, June 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....[10] Switching activity needs more careful analysis since it is very much dependent on the data input to the system; it is also quite hard to capture the unwanted switching. There are in general two different approaches to switching estimation: calculation based and simulation based [7] [13]. In the calculation based switching estimator [5] the switching is computed only analysing the structure of the design and using the switching probabilities of the input signals. The switching probabilities are propagated trough the whole design using some specific transfer function for each ....

R. S. Martin, J. P. Knight, "Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level," Proceeding of DAC 1995.

....pipelining. Architecture Driven Voltage Scaling is a phrase that categorizes techniques that trade off architectural choices against supply voltage. A number of researchers have developed systems or proposed methods that incorporate architecture driven voltage scaling [2] 3] 4] 5] 6] [7], 8] 9] 10] Many of these systems [2] 3] 4] 5] 6] 9] also minimize switching activity in the datapath. Most voltage scaling approaches require that the IC operate at a single supply voltage. Although substantial energy savings can be realized with a single minimum supply voltage, ....

R. SanMartinand J. P. Knight, "Power-profiler: Optimizing ASICs power consumption at the behavioral level," in Proc. 32nd Design Automation Conference, 1995, pp. 42--47.

....path could operate at still lower voltages if multiple voltages were allowed. Even along a critical path, the lowest power solution can require multiple voltages. A number of researchers have developed systems or proposed methods that trade off voltage and power dissipation against circuit area [3, 14, 15, 10, 11, 12, 16, 7]. HYPER LP [3] is a system that transforms the data flow graph of an algorithm to optimize it for low power. Most other systems accept the algorithm as given and apply a variety of techniques during scheduling, module selection, resource binding, etc. to allow reduced supply voltages and minimize ....

R. S. Martin and J. Knight. Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level. In Proceedings 32nd Design Automation Conference, pages 42--47, 1995.

....Voltage Scaling is a name applied to this approach. A number of researchers have developed systems or proposed methods that incorporate architecture driven voltage scaling [Chandrakasan et al. 1995; Raghunathan and Jha 1994; Raghunathan and Jha 1995; Goodby et al. 1994; Kumar et al. 1995; SanMartin and Knight 1995; Raje and Sarrafzadeh 1995; Gebotys 1995] HYPERLP [Chandrakasan et al. 1995] is a system that applies transformations to the data flow graph of an algorithm to optimize it for low power. Other systems accept the algorithm as given and apply a variety of techniques during scheduling, module ....

SanMartin, R. and Knight, J. P. 1995. Power-profiler: Optimizing ASICs power consumption at the behavioral level. In Proceedings, 32nd Design Automation Conference (1995). pp. 42--47.

....minimizing the transitions of their input operands. Kumar et al. [38] measure activities of operations and carriers in a behavioral specification by simulating the DFG with user supplied profiling stimuli. They select a module set and schedule that minimize the switching activity. Martin and Knight [58] applied several low power techniques in behavioral synthesis including lowering supply voltage, disabling the clock of idle components, and architectural trade off. 6.4 HLS for Reliability In many critical applications, fault tolerance is very important. It is desirable that a system is capable ....

R. San Martin and J. P. Knight, "Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level," Proceedings of the Design Automation Conference (DAC), pp. 42-47, 1995.

....allocation as proposed in [6] to increase the temporal correlation, thereby reducing switching activity. In [7] redundant adders are added to reduce the output activity. 8] and [9] introduce coding techniques for reducing the switching activities on the I O pins and address busses. 10] and [11] provide optimum supply voltage and or mixed voltages to the modules. Software may be compiled so as to minimize the power dissipation when it is executed on a given hardware platform, as in [12] In this paper, we demonstrate power reductions at the behavioral level through functional ....

R. Martin & J. Knight, "Power-profiler: optimizing ASICs power consumption at the behavioral level," Proceedings of the Design Automation Conference, pp. 42-47, 1995.

....by making use of two supply voltage levels. The idea is to operate gates on the critical paths at the higher voltage level and the gates on the non critical path at the lower voltage level. In this manner, the energy consumption is minimized without affecting the circuit speed. Power Profiler [8] primarily uses a genetic search algorithm to solve the multiple voltage scheduling problem. Johnson and Roy presented an ILP based formulation for the multiple voltage scheduling problem for non pipelined design in [9] Both algorithms have exponential worst case complexity and hence the results ....

R. Martin and J. Knight, "Power Profiler: Optimizing ASICs power consumption at the behavioral level," in Proceedings IEEE-ACM Design Automation Conference, 1995.

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R. S. Martin and J. P. Knight. " Power-profiler: optimizing ASICs power consumption at the behavioral level. " In Proceedings of the 32nd Design Automation Conference, pages 42-47, June 1995.

No context found.

R. S. Martin and J. P. Knight. " Power-profiler: optimizing ASICs power consumption at the behavioral level. " In Proceedings of the 32nd Design Automation Conference, pages 42-47, June 1995.

No context found.

R. S. Martin and J. P. Knight, "Power profiler: Optimizing ASICs power consumption at the behavioral level," in Proc. Design Automation Conf., June 1995, pp. 42--47.

No context found.

R.S. Martin, J.P. Knight "Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level" Proceedings of DAC, 1995, pp. 42-47.

No context found.

R.S. Martin, J.P. Knight "Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level" Proceedings of DAC, June 1995, pp. 42-47.

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