J. Kuskin et al, The Stanford FLASH Multiprocessor, Intl. Symposium on Computer Architecture, pp. 302-313, April 1994. Home/Search Document Not in Database Summary Related Articles Check |
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Adaptive Line Size Cache - Tang, Veidenbaum, Nicolau, Gupta (Correct)
....throttling for interconnection networks [4] 16] shows that optimal limit varies and suggests admitting messages into the network adaptively based on current network behavior. Adaptive cache control or coherence protocol choices were proposed and investigated in the FLASH and JUMP 1 projects [6, 14]. Adapting branch history length in branch predictors was proposed in [10] since optimal history length was shown to vary significantly among programs. Adaptive adjustment of data prefetch length in hardware was shown to be advantageous [5] while in [8] the prefetch lookahead distance was ....
J. Kuskin et al, The Stanford FLASH Multiprocessor, Intl. Symposium on Computer Architecture, pp. 302-313, April 1994.
Adapting Cache Line Size to Application Behavior - Veidenbaum, Tang, Gupta.. (1999) (16 citations) (Correct)
....throttling for interconnection networks [3] 13] show that optimal limit varies and suggest admitting messages into the network adaptively based on current network behavior. Adaptive cache control or coherence protocol choice were proposed and investigated in the FLASH and JUMP1 projects [5, 12]. Adapting branch history length in branch predictors was proposed in [8] since optimal history length was shown to vary significantly among programs. Adaptive adjustment of data prefetch length in hardware was shown to be advantageous [4] while in [6] the prefetch lookahead distance was ....
J. Kuskin et al, The Stanford FLASH Multiprocessor, Intl. Symposium on Computer Architecture, pp. 302-313, April 1994.
Programming Shared Virtual Memory on the Intel Paragon .. - Berrendorf, Gerndt.. (1995) (1 citation) (Correct)
....MaX which is similar to MYOAN is done at the Technical University Munchen [15] There are some research projects ongoing as well as commercial products available which implement a single address space on a distributed memory computer using dedicated hardware. Among them are Flash at Stanford [11], Alewife at MIT [12] SPP1000 of Convex Computer Corp. 13] and KSR 1 of Kendall Square Research [7] 7 Status and Future Work Currently, the SVM Fortran compiler and ASVM are stable prototypes which have been used to implement several application codes. Performance analysis for these ....
J. Kuskin et al., The Stanford FLASH Multiprocessor, Proc. 21st Int. Symposium on Computer Architecture, pp. 302-313, 1994
Informing Memory Operations: Providing Memory Performance.. - Horowitz (1996) (26 citations) (Correct)
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J. Kuskin, D. Ofelt, M. Heinrich, et al. The Stanford FLASH Multiprocessor. Proc. 21st Annual Int'l. Symposium on Computer Architecture, pp 302--313, April 1994.
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