L. Kontothanassis, M. Scott, "Distributed Shared Memory for New Generation Networks," University of Rochester Technical Report 578, March 1995. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Distributed Shared Memory Using Reflective Memory: The LAM System - Roger Denton (Correct)
....improvements in the consistency model. In [Li89] it is stated that one of the most fundamental design decisions made in the development of a DSM system is the choice of a consistency policy. Nit91] provides an intuitive definition of major consistency models. 2. 1 DSM Performance Improvement In [Kon95] a seemingly obvious conclusion is stated, DSM systems perform better with hardware assist. In this particular case they were working with the Cashmere system [Kon95] and a variety of network interfaces that allowed the shared memory to be mapped into the address space of the cooperating ....
....of a consistency policy. Nit91] provides an intuitive definition of major consistency models. 2.1 DSM Performance Improvement In [Kon95] a seemingly obvious conclusion is stated, DSM systems perform better with hardware assist. In this particular case they were working with the Cashmere system [Kon95] and a variety of network interfaces that allowed the shared memory to be mapped into the address space of the cooperating processors. The authors of TreadMarks [Kel94] quantify the overhead incurred with interfaces that are not mapped into the local address space (e.g. ATM, Ethernet, The ....
L. Kontothanassis, M. Scott, "Distributed Shared Memory for New Generation Networks," University of Rochester Technical Report 578, March 1995.
Hiding Communication Latency and Coherence Overhead in Software.. - Bianchini (1996) (31 citations) Self-citation (Kontothanassis) (Correct)
....abstraction with custom, highly integrated support for cache coherence [19, 1, 18, 21] our design builds mainly upon off the shelf workstation parts and low cost commercial networks. In contrast with systems that maintain cache coherence entirely in software [23] or with hardware support [17, 22], our system does not stress the communication medium and therefore is appropriate for low cost, PCI based networks exhibiting relatively high latency and low bandwidth. Thus, we conclude that our design provides a low cost, quick design time alternative for shared memory computing. Based on this ....
....is consistent with our results. However, the application speedups they present in the paper are superior to the ones we found in our Base experiments. The main reason for this difference is that simulation time limitations prevented us from using inputs as large as theirs. Kontothanassis and Scott [17] propose the Cashmere DSMs, which require the same type of hardware support as AURC. We believe that our claims and results regarding AURC apply to the Cashmere protocols as well. 7 Summary and Conclusions In this paper we addressed the performance implications of using simple protocol ....
L. I. Kontothanassis and M. L. Scott. Distributed Shared Memory for New Generation Networks. In Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, February 1996.
High Performance Software Coherence for Current and Future .. - Kontothanassis, Scott (1994) (6 citations) Self-citation (Kontothanassis Scott) (Correct)
....Princeton Shrimp [4] In comparison to hardware coherent machines, NCC NUMAs can more easily be built from commodity parts, with only a small incremental cost per processor for large systems, and can follow improvements in microprocessors and other hardware technologies closely. In another paper [20], we show that NCC NUMAs provide performance advantages over DSM systems ranging from 50 to as much as an order of magnitude. On the downside, our NCC NUMA protocols require the ability to control a processor s cache explicitly, a capability provided by many but not all current microprocessors. ....
L. I. Kontothanassis and M. L. Scott. Distributed Shared Memory for New Generation Networks. TR 578, Computer Science Department, University of Rochester, March 1995.
Efficient Shared Memory with Minimal Hardware Support - Kontothanassis, Scott Self-citation (Kontothanassis Scott) (Correct)
....differ in terms of: ffl The mechanism used to implement write through to remote memory. Some NCC NUMA hardware will not write through to remote locations on ordinary store instructions. In such cases we can achieve write through by editing program binaries to include special instruction sequences [8], in a manner reminiscent of the Blizzard [19] and Midway [23] projects. ffl The existence of a write merge buffer. If neither the processor nor the cache controller includes a write buffer capable of merging writes to a common cache line (with per word dirty bits for merging into memory) then ....
....and the thesis work of Karin Petersen [15, 16] It is also related to ongoing work on the Wind Tunnel [19] and the Princeton Shrimp [1] project and, less directly, to several other DSM and multiprocessor projects. Full protocol details and comparisons to related work can be found in other papers [8, 9, 10]. 2 Results and Project Status We have evaluated the performance of NCC NUMA hardware running Cashmere protocols using execution driven simulation on a variety of applications. The applications include two programs from the SPLASH suite [20] mp3d and water) two from the NASA parallel ....
[Article contains additional citation context not shown here]
L. I. Kontothanassis and M. L. Scott. Distributed Shared Memory for New Generation Networks. TR 578, Computer Science Department, University of Rochester, March 1995. Submitted for publication.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC