K. Y. Yun, D. L. Dill, and S. M. Nowick. Practical generalizations of asynchronous state machines. In Proceedings of The European Conference on Design Automation with The European Event in ASIC Design, pages 525--530. IEEE Computer Society Press, February 1993.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....developed a collection of tools (known as MEAT) which generate schematic diagrams at the complex gate circuit level from state transition diagrams. A similar approach for the automatic synthesis of asynchronous finite state machines has been used by Nowick, Dill and Yun [Nowi91] Nowi91a] Yun92] [Yun92a]. 5.2.1 CSP based Modelling Approaches The Communicating Sequential Processes (CSP) model of computation has attracted the interest of many researchers as a potential means for the modelling CHAPTER 5. MODELLING ASYNCHRONOUS SYSTEMS 110 of asynchronous designs due to the strong relationship ....

Yun, K. Y., Dill, D. L., Nowick, S. M., "Practical Generalizations of Asynchronous State Machines", Technical Report CSL-TR-92-544, Computer Systems Laboratory, Stanford University, July 1992.

....method, Kishinevsky s change diagrams, is similar to STGs but removes some of the restrictions by adding different types of arcs to the specification. These additional arcs allow more disjunctive behavior to be specified. However, change diagrams have no provision for timing information. Yun [74, 75], Nowick [54] and Coates [25] specify circuits using asynchronous state machines, and perform synthesis using burst mode techniques. The burst mode method allows one signal level to be specified on each arc of the state machine. However, burst mode synthesis requires the fundamental mode ....

....the value of a signal and then making a decision based on the result, is very difficult to specify in purely event based semantics. One specification where a conditional loop is required is the sbuf send pk2 controller from the HP Post Office [25] benchmark suite. This example is cited by Yun in [75] as a motivation for the level extension to burst mode circuits and had to be modified to be expressed as an STG for the SIS benchmark suite. It is also an interesting example of the expressiveness of TEL structures. 1 0 2 3 Req Done Sendline Req Ackline SendlineAckline Done ....

Yun, K. Y., Dill, D. L., and Nowick, S. M. Practical generalizations of asynchronous state machines. In Proc. European Conference on Design Automation (EDAC) (Feb. 1993), IEEE Computer Society Press, pp. 525--530.

....arcs allow disjunctive behavior to be specified. However, change diagrams do not provide a way to model choice, and have no provision for timing information. Other graph based methods specify circuits using asynchronous state machines, and synthesis is performed using burst mode techniques [12, 13, 14, 15]. The burst mode method allows one purely conjunctive expression to be specified on each arc of the state machine. However, burst mode synthesis requires the fundamental mode assumption which states that when a state change occurs, all of the changing outputs are allowed to settle before any ....

....the value of a signal and then making a decision based on the result, is very difficult to specify in a purely event based semantics. One specification where a conditional loop is required is the sbuf send pk2 controller from the HP Post Office [15] benchmark suite. This example is cited in [14] as a motivation for the level extension to burst mode circuits and had to be modified to be expressed as an STG for the SIS benchmark suite. It is also an interesting example of the expressiveness of TEL structures. The purpose of this controller is to manage the transfer of packets between a ....

Kenneth Y. Yun, David L. Dill, and Steven M. Nowick. Practical generalizations of asynchronous state machines. In Proc. European Conference on Design Automation (EDAC), pages 525--530. IEEE Computer Society Press, February 1993.

....3 Timing Analysis of Extended Burst Mode Circuits 3.1 Introduction This chapter describes an interesting application of the min max timing simulation algorithm described in Chapter 2. Specifically, a timing analysis tool for a class of asynchronous circuits, called extended burst mode circuits [105, 103, 99] implemented in the 3D design style [104, 102, 99] a practical asynchronous design style) is described. Given a gate level 3D circuit with bounded gate and wire delays, the tool uses the min max timing simulation algorithm of Chapter 2 to check timing constraints required for correct operation ....

....This section briefly reviews the extended burst mode specification style for asynchronous circuits, and highlights the main characteristics of 3D designs a practical implementation style for extended burst mode specifications. 3.2. 1 Extended Burst Mode Specifications Extended burst mode [105, 103, 99] is a powerful specification formalism that can be used for specifying a large and useful class of asynchronous state machines, synchronous state machines, and systems with both synchronous and asynchronous components. This section reviews some definitions and notations from [99] used later in the ....

K. Y. Yun, D. L. Dill, and S. M. Nowick. Practical generalizations of asynchronous state machines. In Proceedings of The European Conference on Design Automation with The European Event in ASIC Design, pages 525--530. IEEE Computer Society Press, February 1993.

....synthesis path for burst mode circuits using fast optimal algorithms ffl An easily usable environment with a software framework which can readily incorporate new tools Minimalist currently supports widely used plain burst mode [22] 32] specications. Extended burst mode specications [42] will be supported in a forthcoming release. 2 Background and Overview 2.1 Asynchronous Synthesis Asynchronous controller synthesis follows a AEow similar to that of synchronous synthesis; however, it presents unique problems requiring signicantly dioeerent solution methods. Like synchronous ....

K.Y. Yun, D.L. Dill, and S.M. Nowick. Practical generalizations of asynchronous state machines. In EDAC, 1993. 20

....next state functions in two level ANDOR logic. We develop a set of hazard free covering requirements for the 2 level ANDOR implementation of a logic function during an extended burst mode transition. The hazard free combinational logic synthesis for multiple monotonic input changes is described in [23, 5, 3, 4, 53, 77]. The new results presented here are simple extensions of the theory in [53] to account for non monotonic input changes. We apply these results to the 3D machine combinational logic synthesis. Below we state and prove necessary and sufficient conditions for hazard freedom for a two level AND OR ....

K. Y. Yun, D. L. Dill, and S. M. Nowick. Practical generalizations of asynchronous state machines. In Proceedings of The European Conference on Design Automation with The European Event in ASIC Design, pages 525--530. IEEE Computer Society Press, February 1993. BIBLIOGRAPHY 128

....and Computer Science Stanford University Stanford, CA 94305 Abstract We present a design style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed design style not only supports generalized burst mode multiple input change asynchronous designs [21], but also allows the automatic synthesis of any synchronous Moore machine using only basic gates (and no state holding elements) Moreover, the synthesis method covers many circuit styles in the range between burst mode and fully synchronous. We can easily specify and synthesize sequential ....

....signals to edge sensitive signals, often a cumbersomemanual design process, by interfacing directly with level sensitive signals. 1 Introduction Over the last few years, many new design styles and synthesis methods for asynchronous control and interface circuits have been proposed [2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 17, 18, 20, 21]. The high degree of interest in this work stems from designer concerns such as dealing with clock distribution, obtaining high performance, and dealing with interfaces between synchronous and asynchronous devices. There are three loosely defined categories of asynchronous design styles and ....

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K. Y. Yun, D. L. Dill, and S. M. Nowick. Practical Generalizations of Asynchronous State Machines. In EDAC-93.

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