H. Shing and L.M. Ni, "A Conflict-free Memory Design for Multiprocessors", Supercomputing91, pp. 46-55, 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....latency is in both cases the maximum achievable in a given architecture. The mechanism proposed in [10] has the advantage that the addresses of the stream elements do not need to be precalculated before starting the request, and that a cheaper interconnection network than in [9] can be used. In [11] a technique to synchronize the interconnection network in order to allow a conflict free access to cache lines is presented. With this synchronous mode of operation, the memory module that can be accessed by each processor at each cycle is predefined. In fact, these cache lines are streams with ....

....number , this synchronization forces that the memory modules are visited by each processor in lexicographical order. The sequence of allowed requests is repeated every 16 cycles. In general, the period of the synchronization will be M cycles. This type of synchronized access was proposed in [11] to allow a conflict free access to cache lines in scalar multiprocessor systems. Assume that the processors request synchr. cycle j 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 . P 0 SEC 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 . SM 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 P 1 SEC 1 1 1 1 2 2 2 2 3 3 ....

H. Shing and L.M. Ni, "A Conflict-free Memory Design for Multiprocessors", Supercomputing91, pp. 46-55, 1991.

....so that the same access pattern is repeated every M cycles. This arbitration can also be expressed by m(p,q) q mod M pT) mod M (4) Figure 11 Arbitration of the memory accesses for the case P = 4 and T = 4. The idea of arbitrating the accesses to memory in this way was first presented in [21], in which the accesses were performed in this synchronized manner for the special case of accesses to cache lines. Cache lines are a particular case of streams with stride 1, and the length of the cache line was assumed to be a multiple of M. The arbitration of Figure 11 has the following ....

....part of the paper an application of the previous method for one processor to the case of multiprocessors. We propose to arbitrate the access to the memory system so that the memory module that each processor can access at each cycle is pre defined. This kind of synchronization, previously used in [21] for the case of having only requests belonging to cache lines (streams with stride equal to 1) guarantees that conflicts do not occur neither in the interconnection networks nor in the memory modules. The method is valid for systems with l s t and streams with strides of families x = 0, ....

H. Shing and L.M. Ni, "A Conflict-free Memory Design for Multiprocessors", Supercomputing91, pp. 46-55,

....multiplexed links, and are sensitive to virtual channels in the sense that a switch can switch different virtual channels differently. For example, in TDM networks, each switch can be set to different states during different time slots and such a switch is called Time Multiplexed Switch (TMS) [19, 24, 28]. Similarly, there are socalled Wavelength Multiplexed Switches (or WMSs) in WDM networks [5, 25] A more sophisticated switch will be able to transfer information from one virtual channel to another, not just being sensitive to virtual channels. Such switches, for example, are called Time Slot ....

H. Shing and L.M. Ni. A conflict-free memory design for multiprocessor. In Proceedings of Supercomputing, pages 46--55, November 1991.

....as a TST switch does. As a result, the signals arriving at a given input during time slot i will go to an output which depends solely on the switch setting during that time slot. In an S Theta S switch, all possible S 2 connections can be established by multiplexing the switch with degree K = S [28, 29]. However, this may result in an unnecessarily long latency because a given input output connection is established once every S time slots. RTDM provides efficient multiprocessor communications through either static [13] or dynamic [14] reconfiguration which reduces the multiplexing degree K by ....

H. Shing and L. Ni, "A conflict-free memory design for multiprocessor," in Proceedings of Supercomputing, pp. 46--55, Nov. 1991.

....network, processor side) or narrow (fanout at the end of the network, memory side) The authors results show that wide fanout gives better performance than narrow fanout, and that an equal number of memories and (total) processors ports is of little value for supercomputer design. Shing and Ni [11] address the problem of memory and interconnection network contention by essentially time multiplexing physical resources (network switches and memory modules) Each user of a physical resource has a designated time slot in which it can use the resource. Robbins and Robbins [10] solution to ....

Honda Shing and Lionel M. Ni. A Conflict-Free Memory Design for Multiprocessors. In Proceedings of Supercomputing'91, pages 46--55, Albuquerque, New Mexico, November 18--22, 1991.

....that, as a result, the output, which the signals arriving at time t at a given input will go to, depends solely on the switch setting at time t. Just as shown in the example, for an S Theta S switch, all possible S 2 connections can be established by multiplexing the switch with degree K = S [22, 23]. However, this may result in an unnecessarily long latency because a given input output connection is established once every S time slots. RTDM provides efficient multiprocessor communications through either static [13] or dynamic [14] reconfiguration which reduces the multiplexing degree K by ....

H. Shing and L. Ni, "A conflict-free memory design for multiprocessor," in Proceedings of Supercomputing, pp. 46--55, Nov. 1991.

....mentioned in the previous section. From this point, the term shared memory multiprocessors will be used to denote both logically and physically shared memory multiprocessors. 1. 3 Dissertation Outline This dissertation introduces the Conflict Free Memory (CFM) architecture for multiprocessors [9]. Most memory system designs are based on word accesses. In contrast, 6 the CFM architecture is based on block accesses. For multiprocessors within a certain scale range, the architecture eliminates memory and network contention as well as the hot spot problem without increasing latency and ....

H. Shing and L. M. Ni, "A conflict-free memory design for multiprocessors," in Proceedings of Supercomputing '91 Conference, pp. 46 -- 55, Nov. 1991. 121

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H. Shing and L.M. Ni, "A Conflict-free Memory Design for Multiprocessors", Supercomputing91, pp. 46-55, 1991.

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H. Shing and L.M. Ni, "A Conflict-free Memory Design for Multiprocessors", Supercomputing91, pp. 46-55,

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