J.A. Waicukauski et al. Fault simulation for structured VLSI. In VLSI Systems Design, Dec. 1985.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....not every time before a circuit is fault simulated. Our program performs parallel pattern simulation using our eleven value logic algebra to determine the logic value on each wire in time frames 1 and 2 in the fault free circuit. Then, we perform PPSFP (parallel pattern single fault propagation) [4] only in time frame 2 to determine the stuck at 0 and stuck at 1 detectability of the wires. If a stuck at 0 on a wire is detectable in time frame 2 and the wire is logic 0 in time frame 1, then our program checks for possible transient paths to Vdd and computes the DeltaQ wiring in equation 3.1 ....

J.A. Waicukauski et al. Fault simulation for structured VLSI. In VLSI Systems Design, Dec. 1985.

....region, and dynamically ordering faults to place potentially detected faults in separate fault groups [16] The resulting fault simulator, HOPE, is about twice as fast as PROOFS, which is partially due to improvements in implementation. The parallel pattern single fault propagation algorithm [17] for combinational circuits has been extended to synchronous sequential circuits in the fault simulators PARIS [18] and PSF [19] For each group of 32 test vectors, the good circuits is simulated, followed by simulation of a single fault for all 32 vectors. Several iterations may be required ....

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom and T. McCarthy, "Fault simulation for structured VLSI," VLSI System Design, pp. 20--32, December 1985.

....of the total test application time for I testing. DDQ 13th VLSI Test Symposium, pp.317 323, April 1995 4 Leakage Fault Simulation 5 Deterministic Test Generation The simulation algorithm of CURRENT is based on a The deterministic test generation algorithm used in parallel pattern simulation [20] which takes advantage of CURRENT is a combination of a branch and bound the word length of processors used in workstations algorithm [21] 22] with an alternative search method usually 32 bits. The number of patterns simulated in called recursive learning [23] These two test generation parallel ....

Waicukauski, J.A., Eichelberger, E.B., Forlenza, D.O., Lindbloom, E., McCarthy, T. "Fault Simulation for Structured VLSI", VLSI Systems Design, pp.20-32, December 1985

....;FW denote the voltage created by the trapped charge on interconnect open FW when the chip is unpowered, that is, when all other circuit nodes are at GND voltage. Our program lets the user FOREACH 32 vector DO FOREACH interconnect open DO Perform PPSFP (parallel pattern single fault propagation) [22] using the 32 vectors after flipping the fault free logic values on the floating wire created by the interconnect open. FOR vector 1 THROUGH 32 DO IF vector can detect the open THEN Compute the range of trapped charge for this vector to detect the open, and add this range to the detection ranges ....

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and Th. McCarthy. Fault simulation for structured VLSI. In VLSI Systems Design, pages 20--32, Dec. 1985.

....not every time before a circuit is fault simulated. Our program performs parallel pattern simulation using our eleven value logic algebra to determine the logic value on each wire in time frames 1 and 2 in the fault free circuit. Then, we perform PPSFP (parallel pattern single fault propagation) [20] only in time frame 2 to determine the stuck at 0 and stuck at 1 detectability of the wires. If a stuck at 0 on a wire is detectable in time frame 2 and the wire is logic 0 in time frame 1, then our program checks for possible transient paths to Vdd and computes the DeltaQ wiring in Equation 1 ....

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and Th. McCarthy. Fault simulation for structured VLSI. In VLSI Systems Design, pages 20--32, Dec. 1985.

....phase of test pattern generation is the random phase: We use the logic word operations of the computer to simulate 32 pseudo random patterns against one target fault. The simulator is modeled after the parallel pattern, single fault propagation (PPSFP) simulator reported by Waicukaski et al. [18]. In this way we generate patterns for the easily tested faults (generally 80 to 99 of the total faults) When one complete PPSFP pass produces fewer than a predetermined number of patterns (currently two) the second phase, algorithmic pattern generation, begins. The algorithmic test pattern ....

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

....N . Note that a given target fault repeats itself in every time frame, thus mapping the problem onto a multiple stuck at combinational ATPG. A two stage test generation is carried out as follows. a) Random test patterns are applied to circuit CN , and Parallel Pattern Single Fault Propagation [13] is used to cover some of the remaining faults. Note that a test pattern that detects a fault is actually a test sequence with N vectors. Random simulation is continued until a predetermined number of random patterns do not detect any fault. b) For each remaining fault a CNF formula is extracted ....

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Systems Design, VI:20--32, 1985.

....above only once, not every time a circuit is fault simulated. Our program performs parallel pattern simulation using our elevenvalue logic algebra to determine the logic value on each wire in time frames 1 and 2 in the fault free circuit. Then, we perform parallel pattern single fault propagation [4] only in TF2 to determine the stuck at 0 and stuck at 1 detectability of the wires. If a stuck at 0 on a wire is detectable in TF 2 and the wire is logic 0 in TF 1, then our program checks for possible transient paths to Vdd and computes the DeltaQ wiring in Equation 3.1 for the p network breaks ....

J.A. Waicukauski et al. Fault simulation for structured VLSI. VLSI Systems Design, Dec. 1985.

....the output of the fault block is sensitized to the back wire. 2 III. Two Bridge Fault Simulation Methods We implemented two methods of bridge fault simulation and used each of them in the Nemesis ATPG system [7, 11] Nemesis uses parallel pattern, single fault propagation (PPSFP) simulation [14] for pre simulation and single pattern, single fault propagation (SPSFP) simulation after algorithmic vector generation. We place great emphasis on incorporating methods of bridge fault simulation into the PPSFP model, but we will report on parallel and single pattern simulation. While stuck at ....

J. A. Waicukauski, E. B. Eichelberger, D.O.Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

....parameters. The V IDDQ 0 , VL0 , VL1 , and V IDDQ1 points are marked using I DDQ;th = 50 A. 4 Fault Simulation Algorithm The very top level structure of our algorithm is as follows: FOREACH 32 vector DO FOREACH interconnect open DO Perform PPSFP (parallel pattern single fault propagation) [22] using the 32 vectors after flipping the fault free logic values on the floating wire created by the interconnect open. FOR vector 1 THROUGH 32 DO IF vector can detect the open THEN Compute the range of trapped charge for this vector to detect the open, and add this range to the detection ranges ....

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and Th. McCarthy. Fault simulation for structured VLSI. In VLSI Systems Design, pages 20--32, Dec. 1985.

....of the propagation. If a fault further down the fault list introduces a discrepancy onto the same wire, it can immediately be determined whether or not the discrepancy can be propagated. Our bridge fault simulation is done in parallel and is modeled after the PPSFP simulator of Waicukauski et al. [14]. Note that, given the PBF for a bridge, the bridge value for each of the parallel patterns is evaluated in the same fashion as that of any other gate (each of which can perform an arbitrary combinational function) In parallel bridge fault simulation, faults can be propagated from both of the ....

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

....in C. If f is detected, it is dropped from the fault list. This is referred to as single fault propagation [8] Vectors in the input list are simulated consecutively. One may use multiple bits in a data word to simulate patterns in parallel, as in parallel pattern single fault propagation (PPSFP) [9]. PPSFP is one of the fastest fault simulation algorithms for combinational circuits. In a data parallel simulation algorithm, each processor in the system simulates the entire circuit and executes the entire simulation algorithm [4, 7] For fault simulation, one may partition either the vector ....

J. A. Waicukauski and et al, "Fault simulation for structured VLSI," VLSI Systems Design, pp. 20--32, Dec. 1985.

....bits in a data word are used to simulate multiple faults simultaneously. We implemented fault simulation algorithms for both combinational and sequential circuits. Combinational Circuits We implemented both parallel pattern and parallel fault algorithms. Parallel pattern single fault propagation [9](PPSF) known to be a very efficient algorithm to simulate combinational circuits, was the parallel pattern algorithm implemented. Several implementations are possible for parallel fault simulators [1] We use propagation techniques to accelerate fault simulation. Sequential Circuits In sequential ....

J. A. Waicukauski et al, "Fault simulation for structured VLSI," VLSI Systems Design, pp. 20--32, Dec. 1985.

....X and U signal values, hence we need a PP 4 valued signal model. The SP 4valued truth tables can be derived from the 5 valued tables by eliminating the rows and columns for U (or X) and setting all X s in the rows and columns for X (or U) to U. For a PP encoding of 2 valued signals like in [6] [8] 10] one bit is required for each signal value, hence n signal values can be encoded into one n bit computer word. Logic gate evaluations can straightforwardly be performed by using the bitwise parallel primitive computer operations. PP encoding of a 4 valued signal x requires two bits, x ....

....FOS output) is processed only after all higher leveled (i.e. closer to GPOs) FFRs that paths from f pass through have been processed. This maximizes the reuse of information gathered for one FFR by other FFRs. Another line of FS development lead to Parallel pattern single fault propagation (PPSFP) [6]. Here the bits in a computer word and the bitwise parallel primitive computer operations are exploited to evaluate vectors of gate output values in parallel. The concept has been explained in Subsection 2.4. In addition, in [6] efficient fault propagation techniques are introduced, which try to ....

[Article contains additional citation context not shown here]

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and T. McCarthy, "Fault Simulation for Structured VLSI", VLSI Systems Design, pp. 20-32, Dec. 19985.

....only once, not every time before a circuit is fault simulated. Our program performs parallel pattern simulation using the eleven value logic algebra to determine the logic value on each wire in time frames 1 and 2 in the fault free circuit. Then, PPSFP (parallel pattern single fault propagation) [41] 28 simulation is performed only in time frame 2 to determine the stuck at 0 and stuck at 1 detectability of the wires. If a stuck at 0 on a wire is detectable in time frame 2 and the wire is logic 0 in time frame 1, then the simulator checks for possible transient paths to Vdd and computes the ....

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and Th. McCarthy. Fault simulation for structured VLSI. In VLSI Systems Design, pages 20--32, Dec. 1985.

....HP 0.6 process parameters. The V iddq0 , VL0 , VL1 , and V iddq1 points are marked using I ddq;th = 50 A. 4 Fault Simulation Algorithm The top level structure of our algorithm is as follows: FOREACH 32 vector DO FOREACH interconnect open DO Perform parallel pattern single fault propagation [17] after flipping the Wave D0:A0:qg 30f 20f 10f 0 10f 20f 30f 0 1 2 3 Voltage on input a (V) Panel 1 V L0 V L1 V iddq0 V iddq1 Figure 3: Charge on the a input of a NAND gate. fault free logic value on the floating wire. FOR vector 1 THROUGH 32 DO IF vector can detect the open THEN Compute the ....

J.A. Waicukauski, E.B. Eichelberger, D.O. Forlenza, E. Lindbloom, and Th. McCarthy. Fault simulation for structured VLSI. In VLSI Systems Design, Dec. 1985.

....a bridging fault further down the fault list introduces an error onto the same wire, it can immediately be determined whether or not the fault can be propagated. Nemesis bridging fault simulation is modeled after the Parallel Pattern Single Fault Propagation (PPSFP) simulator of Waicukauski et al. [24]. Note that, given the PBF for a bridge, the bridge value for each of the parallel patterns is evaluated in the same fashion as that of any other gate (each of which can perform an arbitrary combinational function) In parallel bridging fault simulation, faults can be propagated from both of the ....

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

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J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

No context found.

J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Design, VI:20--32, 1985.

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J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault simulation for structured VLSI. VLSI Systems Design, pages 20--32, 1985.

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