J. P. Shen, W. Maly, F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers, Vol. 2, No. 6, pp. 13-26, December 1985.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....b are considered only to the purpose of comparison. In such circuits, we will suppose that data, control and multiplexer output drivers have the same transistor sizing. The choice of the fault set, of course, requires the knowledge of the actual IC s layout and the use of inductive fault analysis [10] based tools. To be independent from it, we will consider all the possible resistive bridgings [11] between: a) the nodes belonging to a multiplexer (including its input and output nodes) b) the internal nodes of a multiplexer; c) the input output signals of another multiplexer. For each fault, ....

J. Shen, W. Maly, and F. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design & Test, pp. 33 -- 26, Dec. 1985.

....mentioned above. With the goal to prove a certain fault coverage it can be observed that the analogue defect oriented testing gains an increasing industrial relevance. But, although the underlying concepts and investigations on tools for fault modelling ( 85FantM] 91Ohle] fault listing ([85ShenMF], 96Ohle] 99HoffSM] and fault simulation ( 00StraMV] 98HoffB] 99BartB] are highly developed these approaches are seldom used for more than the calculation of an additional test quality measure after the traditional tests have been determined. Unlike in the digital domain, so far neither ....

Shen, M., J.P., Maly, W., Ferguson, F.J.: "Inductive Fault Analysis of MOS Integrated Circuits", Design & Test of Computers, pp. 13-26, 12, 1985.

....5b) and all faults were detected. The resulting five vectors are shown in Table 1, where the column labeled TV is the test vector number. 3. 3 Layout Based BFs By taking into account the chip physical design, a substantial reduction in the number of realistic BFs can be achieved [19] 22] [31], 32] However, this information is not available to us as it is confidential to each vendor. In this paper, the targeted fault set consists of all possible internal and external BFs within the CLB and, so, represents the worst case scenario. Realistic BF information would likely greatly reduce ....

# J.P. Shen, W. Maly, and F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers, vol. 2, no. 6, pp. 13-26, Dec. 1985.

....of Bridging Faults . 7 Results for Test Point Insertion in Benchmark Circuits . 12 1. INTRODUCTION A common physical defect in MOS technologies is a short between two signal lines which results in a bridging fault [Shen 85] Ferguson 88] Detecting bridging faults during the test process is very important for achieving high quality levels. Bridging faults can be detected with either IDDQ testing [Levi 81] Acken 83] or conventional voltage testing. IDDQ testing involves monitoring the quiescent power supply ....

Shen, J.P., W. Maly, and F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEEDesign & Testof Computers, pp. 13-26, Dec. 1985.

....defects, likely to occur during IC manufacturing) not just to cover abstract, arbitrary LSA faults. In particular, it has been shown that bridging faults, caused by likely spot defects of extra material, are dominant in CMOS process lines [13,14] The Inductive Fault Analysis (IFA) approach [15] provides a method for realistic fault identification, using the technology, defects statistics and layout information. Since then, several tools for realistic fault extraction have been developed, such as carafe [16] and lift [17] Such tools extracts sets of transistor level realistic faults, ....

J. P. Shen, W. Maly and F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design and Test of Computers, vol. 2, n. 6, pp. 1326, Dec. 1985

....contain any redundant faults with respect to the patterns applied during BIST, thus the logic is fully tested during BIST. 2. 3 Test Point Insertion for Non Feedback Bridging Faults A common physical defect in MOS technologies is a short between two signal lines which results in a bridging fault [Shen 85] Ferguson 88] Although bridging faults are generally more random pattern testable than stuck at faults [Millman 89] examples are shown in [Touba 96c] to illustrate that some bridging faults are much less random pattern testable than stuck at faults. Data is presented which indicates that even ....

Shen, J.P., W. Maly, and F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design & Test of Computers, pp. 13-26, Dec. 1985.

....we start from the transistor level, assuming that most physical defects cause the transistor level electrical failure modes (briefly: failures ) short , open and transistor parameter deviation . This is a common assumption which is backed up by the findings of the inductive fault analysis [19]. The fault model is established on the basis of an examination of the gate level faulty behav ior caused by the named failures. After that for each gate type the (transistorlevel) failures are mapped onto (gate level) model faults. The novelty o f this proceeding lies in the application to the ....

J.P. Shen, W. Maly, F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design & est., vol. 2, no. 6, pp. 1326, 1985.

....by the classified regions [4] The probability of each fault can be estimated from the area of this region. Using the fault probability information a set of tests that exercise the identified faults can be generated and, by testing for the most probable faults first, the test time can be minimised [5, 6]. The use of such techniques to improve both the design and testing procedures for ICs can only become more important in an industry where profitability is the key to long term survival. Previously published work on yield prediction has been based on Monte Carlo methods [7] polygon operations ....

J. P. Shen, W. Maly, and F. J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computor Magazine, pages 13--26, Dec 1985.

....fault (SAF) model. On the other hand, the SAF model which has been rather popular in test quality estimating has not withstood the test of time. It has been shown that high SAF coverage cannot quarantee, high quality of testing, for example, for CMOS integrated circuits [3] 4] [5]. The reason is that the SAF model ignores the actual behaviour of digital circuits implemented as CMOS integrated circuits, and does not adequately represent the majority of real IC defects and failure mechanisms. Physical defects that may occur in real circuits often do not manifest themselves ....

....than regions that are separated by a large distance. We assume that every defect that results in a short can be x 1 x 2 x 3 y x 1 x 2 x 3 y approximated by a circle. To estimate the probabilities of shorts between pairs of nodes we use the concept of critical area for shorts [5]. The critical region for shorts is such a region in the circuit that if the center of a defect of a given radius R is located anywhere inside the critical region, a short between two adjacent conducting regions occurs. The critical area is the area of the critical region. It depends on the shapes ....

J.P.Shen, W.Maly, J.Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design and Test, pp.13-26, 1985.

....of the test to uncover physical defects [2] However, low level test preparation has prohibitive computer costs. Hence, a methodology for test preparation, with affordable computer costs, and aimed at high defect coverage, is necessary. In the past, the Inductive Fault Analysis (IFA) approach [3] opened a way for automatic extraction of realistic fault lists from the IC layout, using the information on the technology and the process line defects statistics. As a consequence, several IFA based tools, like carafe [4] and lift [5] have been developed, for which a probability of occurrence ....

....and lift [5] have been developed, for which a probability of occurrence for each This work has been partially supported by the European Union (EU) under Esprit 7107 Project (Archimedes) fault can be computed, based on the concept of critical area. Failure analysis, carried out by many authors [6, 3], has shown that the classical, single Line Stuckat (LSA) fault model does not accurately represent the likely physical defects, especially in CMOS technologies. However, the industry still uses the LSA model with reasonably good results. In fact, although LSA faults don t represent correctly the ....

J.P.Shen, W. Maly and F.J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design & Test of Comp., vol. 2, no. 6, pp.13-26, Dec., 1985.

....applications of this algorithm can be envisaged. Design rule checking is one obvious example, a moving corner stitching band of width just greater then the largest design rule distance enables detection of all design rule violations. Other notable examples include raster plotting, fault extraction [14], pattern generator tape generation, and bipolar device recognition. The reduced memory requirements eliminate the need to employ multiple corner stitched planes as in Magic [1, 15] thereby avoiding plane cross registering overhead. This is especially convenient in case of strong interactions ....

John P. Shen, W. Maly, and F. Joel Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers 2(6) pp. 13-26 (Dec. 1985).

....X denotes a logical conflict. Changing X to 1 makes Z F16 = Z F5 , so F16 is approximated by B always generates. Given a full set of physical faults, a set of functional faults can be derived, usually without too much difficulty. For example, the work of Shen et al. on inductive fault analysis [14] can be used to supply a comprehensive physical fault list. Conversely, if parametric testing is considered as in I DDQ testing, activation of a functional fault like F16 causes a high current condition which can be detected. In this manner, test generation with accurate lowlevel fault models can ....

J. P. Shen, W. Maly, and F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test, Vol. 2, December 1985, pp. 13-26.

....of fault effects at a low level circuit description. For a given cell library the effects of realistic faults defects are studied in detail for each gate type (including complex gates) for example through the use of an analog simulator like SPICE or through the use of inductive fault analysis [18][19] 2. Building of a fault library. The fault effects investigated in step 1 which cause an increased I are DDQ mapped onto corresponding leakage faults. That means the necessary fault detection conditions on the gate level for each fault effect are determined and stored in the fault library. ....

Shen, J.P., Maly, W., Ferguson, J.F., "Inductive Fault Analysis of MOS Integrated Circuits", IEEE Design & Test of Computers, Vol.2, No.6, pp.13-26, December 1985

....the traditional cost function can affect a routing in three aspects, viz. 1) the net length, 2) the performance and (3) the routing style. As process feature size keeps decreasing and IC chips are becoming more complex, chips are more sensitive to process disturbance. Inductive Fault Analysis [9] reveals that close nets are likely to get shorted because of spot defects, the main local disturbance in fabrication processes. Therefore, from the point of view of defect analysis, the yield of a good routing depends not only on the net itself, but also on the environment of the net. In other ....

J.P. Shen, W. Maly and F. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design and Test of Computers, Vol. 2, pp. 13-26, Dec. 1985.

....I. Introduction Obtaining low IC defect levels requires that the ICs tests have very high levels of fault coverage. Defect simulation experiments have shown that the vast majority of all local defects in MOS technologies cause changes in the circuit description that result in bridges and breaks [8, 13]. Most MOS fabrication technologies have more extra conductor defects than extra insulator defects, which makes accurate detection of bridge faults even more crucial. We use the Carafe fault extractor to extract realistic bridge faults in CMOS circuits [10] In the rest of the paper we will refer ....

J.P. Shen, W. Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13--26, December 1985.

....the traditional cost function can affect a routing in three aspects, viz. 1) the net length, 2) the performance and (3) the routing style. As process feature size keeps decreasing and IC chips are becoming more complex, chips are more sensitive to process disturbance. Induc tive Fault Analysis [She85] reveals that close nets are likely to get shorted because of spot defects, the main local disturbance in fabrication processes. Therefore, from the point of view of defect analysis, the yield of a good routing depends not only on the net itself, but also on the environment of the net. In other ....

J. P. Shen,W.Maly,andF. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design & Test of Computers, Vol. 2, pp. 13--26, Dec. 1985.

No context found.

J.P. Shen, W. Maly and F.J. Ferguson. Inductive Fault Analysis of MOS Integrated Circuits. IEEE Design and Test of Computers, 2(6):13-26, December 1985.

No context found.

J. P. Shen, W. Maly, and F. J. Ferguson. Inductive fault analysis of MOS integrated circuits. In IEEE Design and Test, Vol. 2, No. 6, pages 13--36, December 1985. 56

....induce detectably abnormal currents, it may not lead to a diagnosis. Furthermore, depending on the capabilities of the equipment in the failure analysis area, one may not be able to e#ectively measure I DDQ . For these reasons, and because bridging faults are believed to be a common defect type [6], 7] the authors have chosen to pursue the application of bridging fault diagnosis in manufacturing diagnosis and debug situations. However, few commercial tools are available that support bridging fault extraction and simulation, especially for very large circuits. It is therefore desirable to ....

J. P. Shen, W. Maly and F. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design and Test of Comput.,vol.2,no. 6, pp. 13--26, Dec. 1985.

....an I DDQ test for a specific fault includes first applying appropriate inputs to the circuit to cause excessive I DDQ , and then measuring I DDQ . Defect simulation experiments show that the vast majority of all local defects in MOS technologies cause bridges, breaks, and transistor stuck ons[16,4]. Some bridges, breaks, and transistor stuck ons are detectable as logical faults, although they may not be detected by specific complete SSF test sets, but others are only detectable as parametric faults. Defects can be undetectable as logical faults and still cause an IC to be unacceptable for ....

J.P. Shen, W. Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13--26, December 1985.

....File Format 82 K. sim File Format 84 L. src File Format 88 M. tdl File Format 89 References 4 1. An Introduction to Carafe 1. An Introduction to Carafe Inductive Fault Analysis (IFA) is a procedure that determines the failures that can occur in a circuit due to the presence of a spot defect[SMF85]. Carafe bloats and shrinks conducting lines and finds the intersection of conductors in different planes to determine how a layout is affected by spot defects. Since the list of faults is generated based on the layout of the circuit, only the realistically possible faults are reported. The first ....

....to target the faults caused by defects during fabrication. The purpose of Carafe is to indicate which faults are likely to occur so that they may be targeted by tests. Unlike what is assumed by traditional stuck at fault models, CMOS IC defects may not be stuck at a certain logic value [GCV80] [SMF85]. The stuck at fault model does not take into account the actual circuit fault and thus often does not model the resulting behavior of many circuit faults. A better way to generate tests is to first locate the circuit faults that can occur in the circuit, determine the behavior of those circuit ....

J.P. Shen, W.Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13--26, December 1985.

....this paper. The change in the circuit s behavior is a behavioral fault. The changes in behavior can be detected as changes in logic function, excess propagation delay, or excess quiescent power supply current (or any combination of these) We use Carafe [Jee91, JF93] an inductive fault analysis [SMF85] tool, to analyze individual cells. Carafe determines which shorts are likely to occur the realistic shorts based on the layout (physical design) of the circuit and the types of defects that occur during the chip s fabrication. We use the defect den1 Carafe Nemesis CShort Spice Hierarchical ....

J.P. Shen, W. Maly, and F.J. Ferguson. Inductive fault analysis of MOS integrated circuits. IEEE Design and Test of Computers, 2(6):13--26, December 1985.

No context found.

J. P. Shen, W. Maly, F. J. Ferguson, "Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers, Vol. 2, No. 6, pp. 13-26, December 1985.

No context found.

S. Shen, W. Maly, and F. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design Test Comput., vol. 2, pp. 13--26, Dec. 1985.

No context found.

J.P. SHEN, W. MALY AND F.J. FERGUSON, "Induc- tive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test of Computers, Vol. 2, No. 6, Dec. 1985, pp. 13-26.

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