J. Rearick, J. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. Int. Test Conf., Oct. 1993, pp. 54-62.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... now required for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an attractive approach because of its suitability for built in self test (BIST) A simple compact circuit such ....

....88] Jee 93] Circuit level models can then be used to more accurately predict the behavior of each bridging fault. Several different methods have been proposed with various tradeoffs between accuracy and simulation time [Acken 88, 91, 92] Lee 91] Hajj 92] Greenstein 92] Maxwell 93] Rearick 93] The drawback of using layout dependent fault modeling is that if the layout changes, then the results are no longer valid. Since test point insertion involves modifying the circuit and hence changing the layout, layout dependent fault modeling is not feasible. For this reason, gate level ....

Rearick, J., and J.H. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. of lnternational Test Conference, pp. 54-62, 1993.

.... The performance of the switch level tools such as SWITEST [12] or the analog simulators like SPICE [6] are not always acceptable, especially if large VLSI circuits have to be analyzed [13] A different family of methods using mixed level or multi level simulation techniques have been proposed in [14] [15] These methods switch from logic simulation to transistor level simulation whenever an unconventional fault is encountered. These methods are relatively accurate but for large circuits they do not run efficiently as discussed in [11] The above shortcomings motivated us to employ the fuzzy ....

Rearick and J. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. of Int. Test Conf., pp. 54-62, 1993.

....conducting transistors. Situations can appear when the value of Z(x,y) is indeterminate. This model describes more accurately the BF which can occur in CMOS technology and it uses lower level structural information then the former wired model. The voting model still has some limitations shown in [4]: non linear transistors are treated as linear resistors and the BF resistance is assumed to be negligible with respect to transistors resistance. Studies and experiments done in [5] show that most of the bridging faults occurring in a CMOS layout have the resistance lower than 500W. Although ....

J. Rearick, J.H. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proceedings of International Test Conference, pp. 54-62, 1993.

....removed from consideration. This partitioning based on logic simulation was followed by further partitioning based on information from stuck at fault simulation [14] assuming a wired OR model of bridge faults. However, the wired OR and wired AND bridge fault models have been shown to be inaccurate [15]. One key aspect of the approaches described in [4] and [8] 10] 16] is that they use information about single stuck at faults to diagnose bridge faults. Since processing of stuck at faults is computationally much simpler than processing of bridge faults, both in terms of fault list sizes and ....

J. Rearick and J. H. Patel, "Fast and accurate CMOS bridging fault simulation," Proc. Int. Test Conf., pp. 54--62, 1993.

....to the gates driving the bridged wires [CL93] An example of this abstraction is shown in Figure 4.2, which illustrates a bridge between two NAND gates. The Boolean function for this two component simulation model can be derived in a number of ways most notably with analog simulation [FL91, RP93] The voting model described above achieves similar results. Two component simulation is effective at modeling imbalanced fights between bridged cells, but it fails to propagate the analog effects downstream. This oversight can be dealt with in two ways. First, we can ignore the downstream analog ....

....input threshold values, which can then be compared to the analog bridge value to determine the behavior of the downstream gates. This technique for simple threshold determination has been implemented in bridge fault simulators using extensions of the voting model and using analog simulation [MA93, RP93] 11 The threshold characterization model assumes that the analog effect of the bridge fault only propagates one level downstream from the fault site. However, the example in Figure 4.3 shows this assumption is not always valid. The output of the NAND gate in Figure 4.3 is reported by SPICE to ....

J. Rearick and J. Patel. Fast and accurate CMOS bridging fault simulation. In Proceedings of International Test Conference, pages 54--62. IEEE, 1993.

....cells are not considered here. However, the breaks in the inter cell areas are covered since they are equivalent to breaks inside cells. 2.3 Circuits Simulations SPICE [11] is a circuit simulator that has high accurate measurement at the circuit level. It has been widely used for some studies [12, 13]. However, this simulator is very slow when it deals with a complex circuit. In this paper, we use SPICE3 for accurate and extensive simulations of cells with injected defects. Since the simulations are exploited for the basic cells, there is no simulating speed problem. It takes about one second ....

J. Rearick and J. H. Patel, "Fast and accurate CMOS bridging fault simulation," in Proc. Int. Test Conf., pp. 54--62, 1993.

....of the circuit inputs. Bridge Fault: A bridge fault is a short between two signal wires in the circuit which are interconnected with a logical behavior specified by a PTbridge tta file [FL91b] There are several existing test pattern generation systems that produce tests for bridge faults [CL93, CL94, MG91, RP93, MA93]. BridgeIDDQ Test: For a bridge fault, any test that causes the two bridged wires to take on opposite logic values in the fault free circuit is an IDDQ test for that fault[FL91a] Logical Test: A logical test for a fault creates a discrepancy between the primary circuit output in the presence of ....

J. Rearick and J. Patel. Fast and accurate CMOS bridging fault simulation. In Proceedings of International Test Conference, pages 54--62. IEEE, 1993.

....the gate level methods have the following problems: 1. The circuit need to be structurally altered for each BF which can be expensive for large circuits with a large number of BFs. 2. An intermediate cell output voltage can be interpreted differently (as logic 1 or 0) by different fanout cells[7, 8], and this Byzantine General s Problem cannot be handled by gate level approaches. 3. Only routing(external) BFs can be handled since the gate internal information is opaque to the gate level simulators. Switch level simulators[9, 10, 11] model a BF as a permanent conducting transistor. They are ....

....results. 2. Repeated electricallevel DC analysis are often done on the same circuit cluster unnecessarily. 3. Feedback bridging faults are not handled. 4. Speed is only practical for mediumsized circuits. Since mixed mode simulators may still be too slow for large circuits, table based simulators[8, 15] were proposed as a time accuracy trade off to the mixedlevel simulators. In a mixed level simulator EPROOFS described in the last paragraph, larger ALVL values lead to more accurate results while smaller ALVL values make simulation faster. However, 13] shows that when setting ALVL to 3, it ....

J. Rearick, and J. H. Patel, "Fast and accurate CMOS bridging fault simulation," IEEE International Test Conference (ITC), pp. 54--62, 1993.

....For large circuits with huge numbers of BFs, this approach may not be applicable. In general, gate level approaches cannot properly handle the Byzantine General s Problem where an intermediate cell output voltage can be interpreted differently (as logic 1 or 0) by different fanout cells[15, 16]. In addition, they can only simulate routing BFs since no information internal to the gate cells is available to the simulator. Switch level simulators[17, 18, 19] model a BF as a permanent conducting transistor. They are applicable if the BFs can be modeled as transistors with allowable strength ....

....and slows down the simulation. The speed of mixed level simulation is only practical for medium sized circuits because of the frequent calls to the time consuming DC analysis subroutines. Since mixed level simulators may still be too slow for simulating large circuits, table based simulators[16, 24] were proposed as a time accuracy trade off to the mixed level ones. In the table based simulators, output voltages of the bridged cells for each possible bridge in a cell library are pre computed with electrical level simulators such as SPICE. The BF simulation thus can be done at the gate level ....

J. Rearick and J. H. Patel, "Fast and accurate CMOS bridging fault simulation," IEEE International Test Conference (ITC), pp. 54--62, 1993.

....as the single stuck at model. A more exact model would assume that the circuit value at the fault site is described in general by a Boolean function of the inputs to the gates driving the bridged wires. This function could be derived in a number of ways two notable methods are analog simulation [12, 22] and the voting model [3, 4] Deriving the Boolean function by simulating the two components with the bridged outputs works well at modeling the upstream components from the fault site, but fails to take into account the possible sensitive behavior of downstream components. An optimistic model ....

....is much more accurate than previous simulators, it still may make errors when accurately predicting the behavior of the faulty circuit requires a timing analysis of the digital logic. There are faster simulators that do EPROOFS like simulation, although they sacrifice some accuracy for speed [18, 22]. There is currently no test pattern generator that implements such sophisticated models. A feedback bridging fault may create an asynchronous sequential circuit in a formerly combinational network. The state of the circuit may prevent stimulation of the fault, or a stimulated fault may cause ....

J. Rearick and J. Patel. Fast and accurate CMOS bridging fault simulation. In Proceedings of International Test Conference, pages 54--62. IEEE, 1993.

No context found.

J. Rearick, J. Patel, "Fast and Accurate CMOS Bridging Fault Simulation," Proc. Int. Test Conf., Oct. 1993, pp. 54-62.

No context found.

J. Rearick and J. H. Patel, "Fast and accurate CMOS bridging faults simulation", in Proc. IEEE International Test Conference, Oct. 1993, pp. 54-62.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC