D. Millman and J. Garvey, "An accurate bridging fault test pattern generator, " in Proc. Int. Test Conf., 1991, pp. 411--418.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... [Storey 91] Perry 92] Gayle 93] Ma 95] In order to achieve the quality levels now required for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an attractive approach ....

Millman, S.D., and J.P. Garvery, Sr., "An Accurate Bridging Fault Test Pattern Generator," Proc. of lnternational Test Conference, pp. 411-418, 1991.

....the fault site voltage by gates fed by the bridged nodes. It is now well accepted that the traditional stuck at fault model is inadequate for modeling bridging faults [5] 6] Most bridging fault simulators use other alternatives for fault modeling, like the wired AND, wired OR, and voting models [7]. Much of the previous work has either used analytical methods [3] to determine the voltages at the bridged nodes and their interpretation by other gates downstream or has used a table based approach [8] in which pre computed tables are used to insert voltages or logic values at the fault site. ....

....and pull down networks and the transistor model parameters, but also on the bridging resistance. Even though bridging faults in CMOS circuits almost always result in recognizable logic values [15] 16] 17] the wired model leads to an incorrect description of the bridging fault, as the example in [7] shows. In [7] a voting model has been proposed that uses a table based approach for deciding the vote. The drawback of this approach is that it neglects the resistance of the bridge, and also ignores the Byzantine General s Problem . The bridging fault simulator proposed by [8] is based on ....

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Steve D. Millman and James P. Garvey, Sr., "An Accurate Bridging Fault Test Pattern Generator," in Proc. Int. Test Conf., 1991, pp. 411-418.

.... In reality, not only do different gates have different thresholds, but each input of a gate has a different threshold [6] 7] It is well known that the stuck at fault model is inadequate for modeling bridging faults [8] 9] Many models have been developed for bridging faults [6] 10] 11] 12] 13][14][15] 16] Most of these fault models assume a zero ohm bridge resistance, but several models assume a resistive bridge [3] 17] 18] 19] 20] As shown in [1] many bridges can have significant resistance. Figure 1 shows the bridging resistance distribution fit to the data in [1] R b is the bridging ....

S. D. Millman and J. P. Garvey, Sr., "An Accurate Bridging Fault Test Pattern Generator," Proc. Int. Test Conf., 1991, pp. 411-418.

....a new method to generate robust test sets for competing bridging faults that maximizes the probability of detection. The inputs to the circuit is generated in a way such that the driving strength is maximized for one of the shorted drivers and minimized for the other, similar to the approach in [18]. A search algorithm is proposed that will find the necessary input assignments to any transistor network that will maximize or minimize the driving strength and thereby generating bridge voltages that will fall outside the region of logically unresolvable intermediate values. A procedure for ....

....for generating objectives that will expose the bridging faults and the modification of a basic test generation procedure to handle multiple objectives for fault activation as described in Section 5. Most previous approaches for test generation under the competing bridge fault model, such as [17][18], are aimed at designs based on standard cells or gate level descriptions and require precomputed strength tables obtained from extensive analogue simulation of each gate type. Our approach requires only the switch level network description and is applicable to any static CMOS circuit design. ....

S. D. Millman and J. P. Garvey, "An accurate bridging fault test pattern generator", in Proc. IEEE International Test Conference, 1991, pp. 411-418.

....a reasonably good coverage of bridging faults, does not lead to DL values as low as 100 ppm; hence, a new strategy needs to be developed. Failure mechanisms in present day CMOS process lines lead to the dominance of extra material failures [9] causing circuit shorts. Therefore, bridging faults [10, 11, 12] are also the main concern in this work. A significant research effort on the impact of bridging (BRI) faults has been carried out by different authors [10, 13, 14, 15, 16] aiming in particular at test pattern generation [11, 17, 18] However, such research does not always consider physical ....

....failures [9] causing circuit shorts. Therefore, bridging faults [10, 11, 12] are also the main concern in this work. A significant research effort on the impact of bridging (BRI) faults has been carried out by different authors [10, 13, 14, 15, 16] aiming in particular at test pattern generation [11, 17, 18]. However, such research does not always consider physical defects or realistic faults (those originated by physical defects) when this is the case, only small dimension circuits are considered. Moreover, some authors highlight particular aspects of the test preparation problem, like comparing ....

S.D. Millman and J.P. Garvey, "An Accurate Bridging Fault Test Pattern Generator", Proc. of Int. Test Conf. (ITC), pp.411418, IEEE, 1991.

....Once the likely nonfeedback shorts were extracted from the physical design of the circuit, we determined their behavior. The two most commonly used methods of modeling shorts are the wired AND and wired OR models. However, neither of these adequately reflects the behavior of shorts in CMOS circuits[Ack88, FL91, MG91]. The logic value of shorted nodes is determined by how strongly each gate tries to force its value on the shorted node. Since the strength of a gate is generally a function of its inputs we must consider all inputs to the gates to determine what the actual logic value will be. We computed the ....

S.D. Millman and J.P. Garvey. An accurate bridging fault test pattern generator. In Proceedings of International Test Conference, pages 411--418. IEEE, 1991.

....circuit description that result in shorts, which do not necessarily behave as single stuck at faults [FM91] Shorts between wires in the interconnect we define here as bridge faults. It is known that tests covering 100 of the testable single stuck at faults may not adequately cover bridge faults [MG91, FL91] 2 In spite of this shortcoming, tests targeted for single stuck at faults in practice cover a large number of bridge faults. This fact can be verified through bridge fault simulation, where an external simulator targeted for bridge faults performs test grading to determine how many ....

....for bridges was new, the assumption that the bridges caused wired AND or wired OR behavior was fairly good. In the dominant technologies of the time (such as TTL) bridges did create wired logic. However, wired logic does not accurately reflect the behavior of static CMOS circuits [AM91, FL91, MG91] For a given CMOS cell library, it is not guaranteed that one of the nmos or pmos network will always determine the fault behavior. An example is shown in Figure 4.1, where the two bridged CMOS NAND gates from a commercial cell library produce a voltage that is not easily declared as logic 1 or ....

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S.D. Millman and J.P. Garvey. An accurate bridging fault test pattern generator. In Proceedings of International Test Conference, pages 411--418. IEEE, 1991.

....of the circuit inputs. Bridge Fault: A bridge fault is a short between two signal wires in the circuit which are interconnected with a logical behavior specified by a PTbridge tta file [FL91b] There are several existing test pattern generation systems that produce tests for bridge faults [CL93, CL94, MG91, RP93, MA93]. BridgeIDDQ Test: For a bridge fault, any test that causes the two bridged wires to take on opposite logic values in the fault free circuit is an IDDQ test for that fault[FL91a] Logical Test: A logical test for a fault creates a discrepancy between the primary circuit output in the presence of ....

S.D. Millman and J.P. Garvey. An accurate bridging fault test pattern generator. In Proceedings of International Test Conference, pages 411--418. IEEE, 1991.

....in the presence of TSBFs [8] In this paper we use the voting model [4] which is a more accurate model, and can describe the behavior of a considerably larger class of CMOS faulty circuits in the presence of TSBFs. For completeness, we discuss the voting model next. This discussion is based on [20]. For more details about the voting model, please refer to [4] In the voting model, when two lines A and B are shorted, the value v(A; B) at the shorted point on application of an input vector T is determined as follows. If T (A) T (B) then V (A; B) T (A) If T (A) 6= T (B) then v(A; B) is ....

....the fault exhibits neither s a 1 behavior nor s a 0 behavior. The effect of the intermediate level at the faulty point on the rest of the circuit is not known. Therefore, using a somewhat pessimistic assumption, we do not drop such faults during diagnosis when we encounter such a situation. AS in [20], the behavior of different faults with different pull down and pull up strengths were precomputed and stored in our algorithm. Same assumptions were used in our calculation. We would like to point out that we are using the same model for modeling the behavior of faulty circuits in the presence of ....

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Steven D. Millman and Sir. James P. Garvey. An Accurate Bridging Fault Test Pattern Generator. In Proceedings of the International Test Conference, pages 411--418, 1991.

....bridges [13, 7, 11] In order to reduce the defects per million of shipped ICs, we must determine both which defects are likely to occur and the behavior of a faulty circuit with such defects. Tests that cover 100 of the testable single stuck at faults may do a poor job of covering bridge faults [12, 6]. Given this information, we must have an accurate and efficient method for generating tests that detect the likely to occur faults. To find meaningful statistics concerning ATPG, we produce a list of realistic bridge faults bridge faults that could be caused by a single defect connecting two ....

....of accuracy, from resistive modeling A B C D Z X Y D C B A X Y Unfaulted Circuit Faulted Circuit Figure 1: A bridge fault creates a fault block. of the transistors [6] circuit analysis of the vote of transistors in series and in parallel [2] the tabular method used by Millmanand Garvey [12], or an analog circuit analysis of the two gates. Table 1 shows three possible PBFs for the introduced fault block from Figure 1. The column labeled ZWAND shows the fault block output if the technology in question follows the wired AND model, the column labeled ZWOR shows the fault block output if ....

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S.D. Millman and J.P. Garvey. An accurate bridging fault test pattern generator. In Proceedings of International Test Conference, pages 411-- 418. IEEE, 1991.

....of TSBFs[7] In this paper we use the voting model[4] which is a more accurate model and can model the behavior of a considerably larger class of CMOS faulty circuits, in the presence of TSBF. For the completeness of the paper, we next discuss the voting model. This discussion is based on [17]. For more detail about the voting model, please refer to [4] In the voting model, when two lines A, B are shorted, the value at the shorted point V (A; B) on application of an input vector T is determined as follows. If T (A) T (B) then V (A; B) T (A) If T (A) 6= T (B) then V (A; B) is ....

....and the number of conducting transistors. For example, in Figure 1, assume that all the transistors are minimum sized, and the n channel transistors are 2.5 times stronger than the p channel transistors(i.e n channel transistors can sink 2. 5 times more current than p channel transistors can source)[17]. If input a is low, and inputs b, c, d and e are high, the ratio Ru R d is 2.5, and R d Ru R d is 0.29. Assume the threshold for logic zero to be 2V out of 5V , i.e ff = 0:4. Therefore, according to the voting model, the logic level at faulty point is 0. On the other hand, if inputs a, b, c ....

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Steven D. Millman and Sr. James P. Garvey. An Accurate Bridging Fault Test Pattern Generator. In Proceedings of the International Test Conference, pages 411--418, 1991.

....Y are shorted. Let R u ( R d ) be the resistance of the pull up ( pull down ) network at X (Y ) Then, the voltage at the shorted point V br = R d R d Ru Theta V dd . In the Voting Model, logic threshold, which is a function of the technology in use, for all gates is assumed fixed (eg 2:5V [25]) If R d R d Ru Theta V dd is less ( greater ) than this threshold the logic value at the fault location is interpreted as 0(1) by all gates driven by it and the TSBF is said to exhibit s a 0 behavior(s a 1 behavior) If R d R d Ru Theta V dd equals the threshold the TSBF is said to ....

....nFETs in series each with channel resistance r may not have a resistance of 2r. The equivalent resistance is encoded in a table and used by our algorithm. Notation #p (#n) represent the number of pFETs (nFETs) in series, and p# (n#) represent the number of pFETs (nFETs) in parallel. In Table 1[25] nfactors ( pfactors ) is the strength of an nFET (pFET) network relative to an nFET(pFET) Thus two nFETs in series (2n) sinks about 63 of the current of one nFET. Table 2[25] is derived fromTable 1 by dividing the pfactors by the strength ratio of a pFET and an nFET assuming a Sigma10 ....

[Article contains additional citation context not shown here]

Steven D. Millman and Sir. James P. Garvey. An Accurate Bridging Fault Test Pattern Generator. In Proceedings of the International Test Conference, pages 411--418, 1991.

.... Menon detailed complete theories and techniques to perform ATPG on bridging faults (including bridging faults that introduced feedback) in combinational circuits exhibiting wired logic behavior [1] However, wired logic does not accurately reflect the behavior of bridges in static CMOS circuits [4, 12, 20]. The wired logic model (wired AND or wired OR) is the easiest model to implement for simulation and test pattern generation; with the exception of feedback, the wired logic model is almost as easy for an ATPG system to deal with as the single stuck at model. A more exact model would assume that ....

.... model describes the fault behavior with an incomplete Boolean function, where some of the bridge s behavior falls within a gray region within which the model fails to give an answer [12] Both of these approaches have been implemented in bridging fault simulators and test pattern generators [12, 20]. A more general model assumes that the analog behavior induced by the fault extends for a certain distance beyond the fault site, after which the circuit behavior is digitally resolvable. The idea that a bridge voltage can be interpreted differently by different downstream gates is known as the ....

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S. D. Millman and J. P. Garvey. An accurate bridging fault test pattern generator. In Proceedings of International Test Conference, pages 411--418. IEEE, 1991.

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D. Millman and J. Garvey, "An accurate bridging fault test pattern generator, " in Proc. Int. Test Conf., 1991, pp. 411--418.

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