P. Maxwell and R. Aitken, "Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds," in Proc. Int. Test Conf., 1993, pp. 63--72.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....[2] Many models have been proposed for bridging faults. At the gate level, these include simple models like the wired AND and wired OR. These models work for technologies for which one logic value is always more strongly driven than the other. Switch level models [3] and the biased voting model [4] are more accurate for CMOS. However, they may be overly pessimistic and frequently predict unknown logic values (X) when the bridge voltages are near gate threshold values. For sequential circuits (non scan or partial scan) due to state information, the X logic values cause many potential ....

....nodes of bridging fault as shown in the shaded region in Figure 1 (a) The logic gates downstream from the bridged nodes can have variable input logic thresholds. Thus, the voltage at a bridged node may be interpreted differently by different gates. This is known as the Byzantine Generals problem [16, 4]. Figure 1 (b) illustrates this. The voltage at the node A ( VA ) is interpreted as a faulty value (0) by gate d and a good value (1) by gate c. In the absence of the Byzantine Generals problem, all logic gates downstream from the node A would interpret the logic value VA as faulty. Thus, for the ....

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P. C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," in Proc. of the IEEE Intl. Test Conf., pp. 63--72, Oct. 1993.

.... for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an attractive approach because of its suitability for built in self test (BIST) A simple compact circuit such as a linear ....

....[Ferguson 88] Jee 93] Circuit level models can then be used to more accurately predict the behavior of each bridging fault. Several different methods have been proposed with various tradeoffs between accuracy and simulation time [Acken 88, 91, 92] Lee 91] Hajj 92] Greenstein 92] Maxwell 93] Rearick 93] The drawback of using layout dependent fault modeling is that if the layout changes, then the results are no longer valid. Since test point insertion involves modifying the circuit and hence changing the layout, layout dependent fault modeling is not feasible. For this reason, ....

Maxwell, P.C., and R.C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," Proc. of International Test Conference, pp. 63-72, 1993. 15

....bridging faults unmodeled. In [18] the bridging resistance was considered in the fault model, but the threshold voltage of gates fed by the bridged nodes was assumed to be V DD 2 for all gate inputs. A method of simulating bridging faults using variable gate logic thresholds has been proposed in [19]. A concept called Parametric Fault Model has been proposed in [3] in which the bridging resistance is taken into account, and instead of propagating a faulty logic value to the primary output, the detectable bridging resistance interval is propagated. However, this model is based on determining ....

P. C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," in Proc Int. Test Conf., 1993, pp.63-72.

.... is well known that the stuck at fault model is inadequate for modeling bridging faults [8] 9] Many models have been developed for bridging faults [6] 10] 11] 12] 13] 14] 15] 16] Most of these fault models assume a zero ohm bridge resistance, but several models assume a resistive bridge [3] 17][18][19] 20] As shown in [1] many bridges can have significant resistance. Figure 1 shows the bridging resistance distribution fit to the data in [1] R b is the bridging resistance and P(R b ) is the bridging resistance distribution function. Since a test for a zero ohm bridge does not guarantee ....

P. C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," Proc Int. Test Conf., 1993, pp. 63-72.

....in CMOS circuits[2] 3] Whereas some of these faults can be modeled by stuck at behavior, electrical level analysis is necessary to handle the majority of these faults. Furthermore, several studies have reported that a great proportion of realistic bridging faults causes feedback (FB) loops [1] 4][5][6] Active FB in combinational circuits may cause oscillatory behavior if the FB loop consists of an odd number of inversions greater than two. This paper presents a method to simulate and generate robust test sets for competing bridging faults that maximizes the probability of detection. 2. ....

P.C. Maxwell and R.C. Aitken, "Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds", Proc. IEEE Int. Test Conference, Oct. 1993, pp. 63-72

....delay testing. In order to model the effects of shorts accurately, electrical level effects, such as intermediate voltage levels and active feedback, must be considered. For instance, several studies have reported that a great proportion of realistic bridging faults causes feedback loops, 1] 2][5][12] Active feedback in combinational circuits may cause oscillatory behavior if the feedback loop consists of an odd number of inversions. Oscillation may cause the fault to be undetected and, consequently, to reduce the overall defect coverage. This paper presents a new method to generate ....

....each competing fault case as logically resolvable or unresolvable. Some efficient methods based on modeling the driving strength have recently been developed for handling conflicts that occur when the outputs of two gates are shorted and for predicting 2 the logic state at subsequent gates [5] [9] 13] Methods based on mixed mode simulation [9] precomputed tables containing data derived from analogue simulations [5] 6] 11] 13] or extended switch level models [7] 10] can successfully handle a subset of bridging fault cases. Unfortunately, none of these approaches is applicable to ....

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P. C. Maxwell and R. C. Aitken, "Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds", in Proc. IEEE International Test Conference, Oct. 1993, pp. 63-72.

....the resistance of the bridge, the bridged lines can have a range of values. The logic gates at the fanout of a bridged node may have varying threshold voltages and may interpret the voltages at the bridged nodes differently. This effect is well known as the Byzantine Generals problem [Acken 92] Maxwell 93] One of the factors that determines the behavior of a bridge that is of growing importance and interest is the resistance of the bridge. Various studies [Renovell 95] Mandava 99] have shown that the resistance of the bridge has a pronounce effect on the behavior of the interconnect bridging ....

P.C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds", Proc. of the IEEE Int. Test Conf., pp. 63-72, Oct. 1993.

....input threshold values, which can then be compared to the analog bridge value to determine the behavior of the downstream gates. This technique for simple threshold determination has been implemented in bridge fault simulators using extensions of the voting model and using analog simulation [MA93, RP93] 11 The threshold characterization model assumes that the analog effect of the bridge fault only propagates one level downstream from the fault site. However, the example in Figure 4.3 shows this assumption is not always valid. The output of the NAND gate in Figure 4.3 is reported by ....

P. Maxwell and R.C. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

....of the circuit inputs. Bridge Fault: A bridge fault is a short between two signal wires in the circuit which are interconnected with a logical behavior specified by a PTbridge tta file [FL91b] There are several existing test pattern generation systems that produce tests for bridge faults [CL93, CL94, MG91, RP93, MA93]. BridgeIDDQ Test: For a bridge fault, any test that causes the two bridged wires to take on opposite logic values in the fault free circuit is an IDDQ test for that fault[FL91a] Logical Test: A logical test for a fault creates a discrepancy between the primary circuit output in the presence of ....

P. Maxwell and R.C. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

....to reduce the fault list, as in [8] These rules are based only on stuck at fault simulation, making the algorithm time efficient. The diagnostic algorithm also guarantees that the Object Fault will remain in the candidate fault list. Modifications required to use it for the Biased Voting Model [18] are addressed in [9] The results obtained from experiments on ISCAS85 [6] and ISCAS89 [5] benchmark circuits are very promising. In most cases the set of faults is reduced to a reasonably small number in a reasonable amount of CPU time. In the next few sections, we discuss the fault model and ....

Peter C. Maxwell and Robert C. Aitken. Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds. In Proceedings of the International Test Conference, pages 63--72, 1993.

....set of rules which are used to reduce the fault list. These rules are based only on stuck at fault simulation making it time efficient. The diagnostic algorithm also guarantees that the Object Fault will remain in the residual fault list. Modifications required to use it for the Biased Voting Model[15] are addressed in the discussion section. The results obtained from experiments on ISCAS85 and ISCAS89 1 benchmark circuits are very promising. In most cases it reduces the set of faults to a reasonably small number in a reasonable amount of CPU time. In next few sections, we first discuss the ....

....used. 7 Discussion We studied the diagnosis problem for bridging faults. The voting model was used to model the behavior of the faulty circuit in the presence of bridging faults. An Algorithm for this problem was discussed. The experimental results obtained are encouraging. In some recent papers[15, 19] some weaknesses of the voting models were pointed out. They are: the resistance of the FET channel is a function of the voltage between the source and drain; and the voltage level at the faulty point could turn on some nFET ( pFET ) while it may not turn on other nFETs ( pFET ) The first is a ....

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P. Maxwell and R. Aitken. Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Threshold. In Proceedings of the International Test Conference, pages 63--72, 1993.

.... (for the C880) and can reach over 200 matches (for the C7552) The MMA theorem guarantees that the correct match will appear in the diagnosis as long as the observed behavior of the fault is not affected by variable logic thresholds, which commonly affect the behavior of faulty CMOS circuits [17, 31]. One of the goals of this research was to investigate the effects of such thresholds on the MMA technique, and ultimately to attempt to compensate for such effects in an improved diagnostic technique. 3.3 The Byzantine Generals Problem for Bridging Faults In order to be detected with a logic ....

P. Maxwell and R. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

.... the voting model to take into account variable drive strengths in CMOS logic gates [1] However, they pointed out that their method did not address the Byzantine Generals Problem for bridging faults [2] Maxwell and Aitken suggested biased voting as a solution to the Byzantine Generals Problem [19], but biased voting fails to simulate all the repercussions of feedback bridging faults, and it fails to take into account input logic thresholds more than one level away from the fault site. Greenstein and Patel suggested using a mixed mode simulator with SPICE level accuracy in a region around ....

P. Maxwell and R. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

....and the information given by SSA fault simulation, resulting in a time efficient algorithm. We also showed how to avoid explicit enumeration of TSBFs. To do that we used a compact representation of TSBFs and implicit enumeration technique making the algorithm space efficient. In some recent papers[22, 27] some weaknesses of the Voting models were pointed out. They are: the resistance of the FET channel is a function of the voltage between the source and drain; and the voltage level at the faulty point could turn on some nFET (pFET) while it may not turn on other nFETs (pFET) The first is a ....

....nFET (pFET) while it may not turn on other nFETs (pFET) The first is a consequence of the well know Vds Ids characteristic of FETs while the second one is a consequence of the variations in threshold voltage of the different FETs. The conductance table we used [16] are correct for Vds near 2. 5V [22]. Our proposed algorithm can be modified to use Biased Voting model. In procedure Reduce, based on different V ds different resistance will be used for consistency checking. For those TSBFs which exhibits multiple stuck at behavior, we can treat them as neither stuck at 0 nor stuck at 1 ....

Peter C. Maxwell and Robert C. Aitken. Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds. In Proceedings of the International Test Conference, pages 63--72, 1993.

.... (for the C880) and can reach over 200 matches (for the C7552) The MMA theorem guarantees that the correct match will appear in the diagnosis as long as the observed behavior of the fault is not affected by variable logic thresholds, which commonly affect the behavior of faulty CMOS circuits [8, 15]. 3 Byzantine Generals Problem In order to be detected with a logic test, a bridging fault must create an error that is propagated to one or more circuit outputs. At the fault site, this error is 1 Throughout this paper we will use the term observed faulty behavior rather than fault signature ....

P. Maxwell and R. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

....the bridge as shown in the shaded region in Figure 1 (a) The logic gates downstream from the bridged nodes can have variable input logic thresholds. Thus the intermediate voltage at a bridged node may be interpreted differently by different gates. This is known as the Byzantine Generals Problem [2, 3] and is illustrated in Figure 1 (b) The voltage at the node A ( VA ) is interpreted as a faulty value (0) by gate d and a good value (1) by gate c. Thus, different branches from a single fanout stem can have different logic values. The feasibility of any diagnosis scheme can be evaluated using ....

....value (1) by gate c. Thus, different branches from a single fanout stem can have different logic values. The feasibility of any diagnosis scheme can be evaluated using the parameters: accuracy, precision, storage requirements and computational complexity. Accurate simulation of bridging faults [4, 3] is computationally expensive. Thus, it may not be feasible to perform bridging fault simulation during diagnosis. Further, the space of all bridging faults is extremely large. For example, for the large ISCAS89 benchmark circuits, it is of the order of 10 9 faults. Several techniques have been ....

P. C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds," in Proc. of the IEEE Intl. Test Conf., pp. 63--72, Oct. 1993.

....is much more accurate than previous simulators, it still may make errors when accurately predicting the behavior of the faulty circuit requires a timing analysis of the digital logic. There are faster simulators that do EPROOFS like simulation, although they sacrifice some accuracy for speed [18, 22]. There is currently no test pattern generator that implements such sophisticated models. A feedback bridging fault may create an asynchronous sequential circuit in a formerly combinational network. The state of the circuit may prevent stimulation of the fault, or a stimulated fault may cause ....

P. Maxwell and R. C. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

No context found.

P. Maxwell and R. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. Proceedings of the International Test Conference, pages 63-72. IEEE, 1993.

No context found.

P. Maxwell and R. Aitken. Biased voting: a method for simulating CMOS bridging faults in the presence of variable gate logic thresholds. In Proceedings of International Test Conference, pages 63--72. IEEE, 1993.

No context found.

P. Maxwell and R. Aitken, "Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds," in Proc. Int. Test Conf., 1993, pp. 63--72.

No context found.

P.C. Maxwell, R.C. Aitken, Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds, Proc. Int. Test Conf. (ITC), pp. 63--72, 1993.

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P. C. Maxwell and R. C. Aitken, "Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds", in Proc.

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