S. Greenstein and J. Patel, "E-PROOFS: A CMOS bridging fault simulator, " in Proc. Int. Conf. Computer Aided Design, 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....values (X) when the bridge voltages are near gate threshold values. For sequential circuits (non scan or partial scan) due to state information, the X logic values cause many potential detections and can degrade diagnosis [5] Multi level simulations that use circuit level (analog) information [6] are accurate. However, these are computationally expensive and cannot be used directly for repeated diagnosis using simulation. Several techniques have been proposed for bridging fault This research was supported in part by Defense Advanced Research Projects Agency (DARPA) under contract DABT ....

....paper. During diagnosis, the failing outputs from the test are used to adaptively determine the behavior of the bridging fault on each time frame, and predict faulty states. Faulty state information is stored at selective state storage points [15] by performing accurate bridging fault simulation [6] once before diagnosis. During diagnosis, the state information is used to increase the accuracy. State storage can have considerably smaller storage requirements than fault dictionaries [15] Further, the combination of adaptive simulation, state storage, and path tracing significantly lowers the ....

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G. S. Greenstein and J. H. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," in Proc. of the IEEE/ACM Intl. Conf. on Computer-Aided Design, pp. 268--271, Nov. 1992.

.... to achieve the quality levels now required for digital integrated circuits, research has been done on deterministic test pattern generation and fault simulation techniques that explicitly target bridging faults [Abramovici 85] Acken 91] Millman 91] Lee 91] Ferguson 91] Hajj 92] Greenstein 92] Chess 93, 94] Rearick 93] Maxwell 93] While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo random testing of bridging faults. Pseudo random testing is an attractive approach because of its suitability for built in self test (BIST) ....

....bridging faults [Ferguson 88] Jee 93] Circuit level models can then be used to more accurately predict the behavior of each bridging fault. Several different methods have been proposed with various tradeoffs between accuracy and simulation time [Acken 88, 91, 92] Lee 91] Hajj 92] Greenstein 92] Maxwell 93] Rearick 93] The drawback of using layout dependent fault modeling is that if the layout changes, then the results are no longer valid. Since test point insertion involves modifying the circuit and hence changing the layout, layout dependent fault modeling is not feasible. For ....

Greenstein, G.S., and J.H. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," Proc. of International Conference on Computer-Aided Design (ICCAD), pp. 268-271, 1992.

.... performance of the switch level tools such as SWITEST [12] or the analog simulators like SPICE [6] are not always acceptable, especially if large VLSI circuits have to be analyzed [13] A different family of methods using mixed level or multi level simulation techniques have been proposed in [14] [15]. These methods switch from logic simulation to transistor level simulation whenever an unconventional fault is encountered. These methods are relatively accurate but for large circuits they do not run efficiently as discussed in [11] The above shortcomings motivated us to employ the fuzzy logic ....

S. Greenstein and J. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," Proc. of Int. Conf. Computer Aided Design, 1992.

....versions of the large ISCAS89 benchmark circuits. Test sets generated by HITEC [22] a deterministic fault oriented test generator, were used. A hundred random nonfeedback bridge faults were injected into each circuit to evaluate the proposed diagnostic procedure. A bridge fault simulator E PROOFS [23] was used to model the faulty device responses. EPROOFS provides electrical level simulation accuracy by performing electrical level simulation in the area around the two bridged nodes. A bridge resistance of 0# and threshold voltages of 1V for NMOS and 1V for PMOS were used in the ....

G. S. Greenstein and J. H. Patel, "E-PROOFS: A CMOS bridging fault simulator," Proc. Int. Conf. Computer-Aided Design, pp. 268-271, Nov. 1992.

....mixed voltage and Iddq testing in order to reduce the number of faults which are not detectable by voltage testing and which therefore must be tested using Iddq techniques. Several mixed mode fault simulators with logic , switch , and electrical level mode have been developed for bridging faults [3, 4, 5]. These simulators use detailed electrical level mode only around the fault locations. For other part of the circuit not affected by the faults, gatelevel or switch level mode are used, which is a good tradeoff between performance and simulation time. But all these simulators ignore timing ....

....up to the point where a fault is injected. At this point, all affected subcircuits switch to electrical mode if necessary and are analyzed using circuit simulation techniques. This continues until the propagated intermediate voltage signals have returned to digital signals in nature similar to [4]. 2.2 Test Vector Selection and Faulty Path Excitation Detection Even with the subset of faults that are left after logic fault simulation is completed, timing simulation of the entire faulty circuit for all the vectors in the test set is still very expensive. Testing the timing behavior of a ....

Gary S. Greenstein, and Janak H. Patel, "E-PROOFS: a CMOS bridging fault simulator," Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp. 268-271, 1992.

....example where threshold characterization may not be valid 4.4 Regional analog simulation A more general model assumes that the analog behavior induced by the fault extends for a certain distance beyond the fault site, after which the circuit behavior is digitally resolvable. The EPROOFS simulator [GP92] implements this within a mixed mode simulator, where a SPICE like analog simulation of the region around the fault site is incorporated into a digital simulation of the rest of the circuit. EPROOFS provides correct answers for many cases, especially those involving feedback or the need for ....

.... simulator that uses a remote interface to SPICE (results are shown for the full SPICE Level 2 MOSFET model) and less accurate but much faster hard coded analog simulator for CMOS circuits, which uses a subset of the SPICE Level 2 MOSFET model, as implemented in the EPROOFS mixed mode simulator [GP92] The EPROOFS model yields results that are less accurate than the full SPICE implementation of the Level 2 model, but it is much faster. It is difficult to compare the relative coverages obtained by the three techniques, because their exact instances of disagreement are unknown. In fact, no ....

G. Greenstein and J. Patel. EPROOFS: a CMOS bridging fault simulator. In Proceedings of International Conference on Computer-Aided Design, 42 pages 268--271. IEEE, 1992.

....voting fails to simulate all the repercussions of feedback bridging faults, and it fails to take into account input logic thresholds more than one level away from the fault site. Greenstein and Patel suggested using a mixed mode simulator with SPICE level accuracy in a region around the fault site [13], but their method fails to account for timing errors introduced by bridges and may not accurately predict when a feedback bridging fault creates latching behavior [22] None of the above schemes address the fact that the resistance of a bridging fault is not a known quantity and may significantly ....

G. Greensteinand J. Patel. EPROOFS: a CMOS bridging fault simulator. In Proceedings of International Conference on Computer-Aided Design, pages 268--271. IEEE, 1992.

....is needed for the I DDQ testing. 2. Even with the existence of BFs, most nodes in a circuit assume voltage values good enough to be interpreted as logic 1 or 0. Therefore logic simulation is accurate enough at those nodes. Due to the above reasons, mixed mode bridging fault simulation methods [13, 14] were proposed for accurate results at higher speed. In [13, 14] switchor gate level simulation is first performed starting with the primary inputs, then electrical level simulation is performed at the bridged cells and their fanout cones for a few levels before the simulation switches back to ....

....of BFs, most nodes in a circuit assume voltage values good enough to be interpreted as logic 1 or 0. Therefore logic simulation is accurate enough at those nodes. Due to the above reasons, mixed mode bridging fault simulation methods [13, 14] were proposed for accurate results at higher speed. In [13, 14], switchor gate level simulation is first performed starting with the primary inputs, then electrical level simulation is performed at the bridged cells and their fanout cones for a few levels before the simulation switches back to switch or gate level. In [13] ALVL, a constant number of levels ....

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G. S. Greenstein and J. H. Patel, "EPROOFS: A CMOS bridging fault simulator," IEEE International Conference on Computer-Aided Design (ICCAD) , pp. 268--271, 1992.

....in a circuit assume voltage values close enough to be interpreted as logic 1 or 0. Therefore logic simulation is adequate at those nodes. Practically, electrical level BF simulation is only applicable to small circuits due to the extremely long computation time. Mixed level BF simulation methods [22, 23] were developed to simulate BFs more efficiently while maintaining the accuracy of electrical level simulators. In these methods, switch or gate level simulation is first performed starting with the primary inputs, then electrical level simulation is performed only at the bridged gates and their ....

....simulators. In these methods, switch or gate level simulation is first performed starting with the primary inputs, then electrical level simulation is performed only at the bridged gates and their fanout cones for a few levels before the simulation switches back to switch or gate level. In [22], a constant number of gate levels for electrical level simulation is used; all unresolved intermediate voltage values are then mapped to logic values. In [23] electrical level simulation remains as long as the gate outputs cannot be interpreted as definite logic 1 or 0. In the mixed level ....

G. S. Greenstein and J. H. Patel, "EPROOFS: A CMOS bridging fault simulator," IEEE International Conference on Computer-Aided Design (ICCAD) , pp. 268--271, 1992.

....value (1) by gate c. Thus, different branches from a single fanout stem can have different logic values. The feasibility of any diagnosis scheme can be evaluated using the parameters: accuracy, precision, storage requirements and computational complexity. Accurate simulation of bridging faults [4, 3] is computationally expensive. Thus, it may not be feasible to perform bridging fault simulation during diagnosis. Further, the space of all bridging faults is extremely large. For example, for the large ISCAS89 benchmark circuits, it is of the order of 10 9 faults. Several techniques have been ....

....sequential benchmark circuits [12] In practice, the failing responses used as input for the diagnosis procedure would be obtained by testing the failing circuit on a tester. For our diagnosis experiments, the failing responses were generated using the accurate bridging fault simulator E PROOFS [4] to ensure that the diagnostic experiments were as realistic as possible. The cell libraries for the circuits were generated manually [4] The test vectors used were compact tests generated to target stuck at faults [13] Ideally, diagnostic test sets for bridging faults would be the best choice. ....

[Article contains additional citation context not shown here]

G. S. Greenstein and J. H. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," in Proc. of the IEEE/ACM Intl. Conf. on ComputerAided Design, pp. 268--271, Nov. 1992.

....extends for a certain distance beyond the fault site, after which the circuit behavior is digitally resolvable. The idea that a bridge voltage can be interpreted differently by different downstream gates is known as the Byzantine Generals Problem for bridging faults [5] The EPROOFS simulator [14] implements this via mixed mode simulation, where a SPICE like analog simulation of the region around the fault site is incorporated into a digital simulation of the rest of the circuit. This method provides correct answers when previous models might have failed, in particular for many cases ....

G. Greenstein and J. Patel. EPROOFS: a CMOS bridging fault simulator. In Proceedings of International Conference on Computer-Aided Design, pages 268--271. IEEE, 1992.

....candidate fault list when the intersection of the three fault lists is taken. 3 Results Experiments were carried out on an HP 9000 J200 with 256 MB RAM to evaluate the proposed fault list reduction procedure. Compact test sets generated by HITEC were used, and the E PROOFS bridge fault simulator [5] was used to model the faulty device responses for 200 random nonfeedback bridge faults in each ISCAS85 benchmark circuit studied. The sizes of the bridge fault lists resulting from the bridge fault reduction procedure are presented in column 4 of Table 1. The percent reduction compared to layout ....

G. S. Greenstein and J. H. Patel, "E-PROOFS: A CMOS bridging fault simulator," Proc. Int. Conf. Computer-Aided Design, pp. 268-271, Nov. 1992.

....research was supported in part by the Semiconductor Research Corporation under Contract SRC 95 DP 109 and in part by DARPA under Contract DABT63 95 C 0069. to 0.18 of the all pair bridging fault set and 4.17 times the number of nodes in the circuit. Second, voltage testing based fault simulation [6] can be performed with a stuck at fault test set on a given reduced fault set to remove bridging faults that can be detected by voltage testing, thus further reducing the size of the fault set that has to be targeted for I DDQ test generation. This technique can be considered as a ....

....targeted for I DDQ test generation. This technique can be considered as a simulation based bridging fault filtering. In our experiments, we have found detection rates of 70 to 90 for a given reduced fault set using a HITEC generated [7] voltage test set with the bridging fault simulator EPROOFS [6]. In addition to fault set reduction, an efficient scheme must be used to incorporate the given reduced fault set into an I DDQ test generator. In [1] 2] a genetic algorithm based I DDQ test generator was developed. Its ability to handle large sequential circuits was based on a built in ....

[Article contains additional citation context not shown here]

G. S. Greenstein and J. H. Patel, "EPROOFS: A CMOS bridging fault simulator," Proc. Int. Conf. Computer-Aided Design, pp. 268--271, 1992.

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S. Greenstein and J. Patel, "E-PROOFS: A CMOS bridging fault simulator, " in Proc. Int. Conf. Computer Aided Design, 1992.

No context found.

G. Greenstein, J. Patel, "E-PROOFS: A CMOS Bridging Fault Simulator," Proc. IEEE/ACM Conf. on Computer-Aided Design, Nov. 1992, pp. 268 -- 271.

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G. Greenstein and J. Patel. EPROOFS: a CMOS bridging fault simulator. Proceedings of the International Conference on Computer-Aided Design, pages 268-271, IEEE, 1992.

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